Impress employers and recruiters.
Choose from hundreds of resume examples.
Impress employers and recruiters.
Choose from hundreds of resume examples.
Tailor your resume to this Principal Design Engineer role.
Rezi rewrites your resume against Cadence Design Systems's job description. Free.
Tailor your resume to this Principal Design Engineer role.
Rezi rewrites your resume against Cadence Design Systems's job description. Free.
Don't guess if your resume is good enough.
See how it scores against the Principal Design Engineer posting at Cadence Design Systems — free, in seconds.
Don't guess if your resume is good enough.
See how it scores against the Principal Design Engineer posting at Cadence Design Systems — free, in seconds.
About the Role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We’re doing work that matters. Help us solve what others can’t.
Responsibilities
- Design and integration of IPs in SoC based on high-level architectural specifications from customers.
- Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
- Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA optimization.
- Create detailed Microarchitectural Specification documents for the design.
- Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
- Provide support to the physical design team as needed for design implementation.
- Implement innovative solutions to automate repetitive tasks.
- Collaborate within and across teams for effective project execution.
Requirements
- B.E./B.Tech/M.Tech with 12+ years of experience as a digital design engineer.
- Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
- Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
- Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
- Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.
- Experience with AMBA protocols and other ARM IPs is a plus.
- Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.
- Proficiency in scripting languages (Python/Perl/Tcl).
- Ability to innovate and automate repetitive tasks.
- Good communication skills for effective cross-functional collaboration.
Skills
- Verilog/SystemVerilog (SV)
- Lint/CDC tools
- Synthesis constraints
- Static Timing Analysis (STA)
- Simulation tools (e.g., Xcelium, Verisium)
- AMBA protocols
- ARM IPs
- High-speed IPs (PCIe, Ethernet, DDR)
- Python/Perl/Tcl scripting
Experience Level
- 12+ years of experience as a digital design engineer
Education Level
- B.E./B.Tech/M.Tech