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About the Role
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s “Intelligent Cloud” mission by delivering core infrastructure and foundational technologies for Microsoft's online businesses. The Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer-focused solutions, insight, and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
Responsibilities
- Provide technical leadership for Memory Subsystem development, driving solutions from architecture and microarchitecture through silicon bring-up.
- Lead the design, integration, and verification of high-performance, complex SoC subsystems, focusing on memory technologies, bandwidth, latency, utilization, power, and overall system efficiency.
- Collaborate with Architecture, RTL Design, DV, Physical Design (PD), Design-for-Test (DFT), Firmware, and Post-Silicon teams to resolve system-level issues and deliver robust silicon.
- Drive vertical and horizontal IP/component reuse across projects and platforms, ensuring scalable and efficient subsystem architectures.
- Provide technical leadership through mentorship, design reviews, code reviews, and cross-functional collaboration, establishing and maintaining engineering best practices.
- Develop and optimize subsystem architectures involving PCIe, HBM, imaging and control subsystems, interconnect fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement.
- Drive design implementation, including microarchitecture specification, RTL development and integration using Verilog/SystemVerilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, lint, and RDC.
- Debug complex design and system-level issues across simulation, emulation, and silicon, identifying root causes and implementing effective solutions.
- Drive execution in an Agile development environment, including sprint planning, feature deployment, code reviews, issue resolution, and continuous improvement of design and verification processes.
- Champion high-quality engineering execution and contribute to delivering cutting-edge, custom IP and SoC solutions that meet demanding performance, power, efficiency, and schedule requirements.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
- Equivalent experience.
- Ability to meet Microsoft, customer and/or government security screening requirements.
- Must pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
- Must provide proof of country of citizenship or US residency or other protected status for assessment of eligibility to access export-controlled information.
- Successful candidate’s citizenship will be verified with a valid passport.
- Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
- 9+ years of experience in RTL design with a proven track record of delivering high-performance IP, SS, or SoC designs such as PCIe, DDR, or HBM.
- Expertise in microarchitecture specification, RTL coding, and design verification collaboration.
- Experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug.
- Experience with design quality and static checks, DFT implementation and hand off to physical design.
- Lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar.
- Experience with lead roles across cross-functional / cross-time-zone engineering teams.
- Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs.
- Experience in Scripting language such as Python or Perl.
Skills
- Memory Subsystem development
- Architecture
- Microarchitecture
- Silicon bring-up
- SoC subsystems design
- Memory technologies
- Bandwidth
- Latency
- Utilization
- Power efficiency
- System efficiency
- RTL Design
- DV
- Physical Design (PD)
- Design-for-Test (DFT)
- Firmware
- Post-Silicon
- IP/component reuse
- Mentorship
- Design reviews
- Code reviews
- Cross-functional collaboration
- Engineering best practices
- PCIe
- HBM
- Imaging subsystems
- Control subsystems
- Interconnect fabrics
- AMBA AXI/CHI protocols
- DMA engines
- NoCs
- High-throughput data buffering
- Data movement
- Verilog/SystemVerilog
- Synthesis
- Timing constraints
- Floor-planning
- Performance optimization
- Design-quality closure
- CDC
- Lint
- RDC
- Simulation
- Emulation
- Silicon debug
- Agile development
- Sprint planning
- Feature deployment
- Issue resolution
- Continuous improvement
- Custom IP
- SoC solutions
- Electrical Engineering
- Computer Engineering
- Computer Science
- RTL design
- High-performance IP
- SS designs
- SoC designs
- DDR
- Microarchitecture specification
- RTL coding
- Design verification
- Power / performance / area (PPA) trade-offs
- Post-silicon debug
- Design quality
- Static checks
- DFT implementation
- CPU IP
- VPU IP
- GPU IP
- Direct Memory Access (DMA) engine
- Tensor unit
- Cross-functional teams
- Cross-time-zone teams
- Artificial Intelligence (AI)
- Machine Learning (ML)
- SoCs
- Scripting language
- Python
- Perl
Experience Level
- 3+ years technical engineering experience
- 6+ years technical engineering experience
- 8+ years technical engineering experience
- 9+ years of experience in RTL design
- Lead experience
Education Level
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Salary/Compensations
- USD $142,800 - $274,800 per year (U.S. typical base pay range)
- USD $188,000 - $304,200 per year (San Francisco Bay area and New York City metropolitan area base pay range)
Benefits
- Certain roles may be eligible for benefits and other compensation.
About the Company
- Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.
- SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.
- Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
- As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance.
Equal Opportunity
- Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
- If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.