Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

Tailor your resume to this Sr. Staff Engineer, Front-End Verification role.

Rezi rewrites your resume against Tenstorrent's job description. Free.

Resume score gauge reading 58 out of 100

Don't guess if your resume is good enough.

See how it scores against the Sr. Staff Engineer, Front-End Verification posting at Tenstorrent — free, in seconds.

About the Role

Contribute to the unit-level verification of our RISC-V CPU front end, focusing on instruction fetch, branch prediction, and related control structures. Build testbenches, generate stimulus, and develop checkers for complex microarchitectural scenarios as a key individual contributor.

Responsibilities

Work within the front-end DV team to build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks.
Develop constrained-random and directed tests targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions.
Help develop and maintain C++ reference models and predictors that integrate into the verification framework for cycle-accurate or transaction-level checking.
Execute verification plans, track functional and code coverage metrics, and ensure edge cases are verified.

Requirements

Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++.
Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking.
Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels.
Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs.

Skills

SystemVerilog
UVM
C++
RISC-V
CPU front-end verification
Instruction fetch
Branch prediction
Testbench development
Stimulus generation
Checker development
Microarchitectural verification
Constrained-random testing
Directed testing
Reference modeling
Transaction-level modeling
Functional coverage
Code coverage
RTL design interaction
Verilator

Location

Austin, TX
Santa Clara, CA

Work Type

Hybrid

Experience Level

Various experience levels considered

Salary/Compensations

$100k - $500k

Benefits

Highly competitive compensation package

About the Company

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.
Solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.
We value collaboration, curiosity, and a commitment to solving hard problems.
We are growing our team and looking for contributors of all seniorities.

Equal Opportunity

We are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.
Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).
These requirements apply to persons located in the U.S. and all countries outside the U.S.
As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.