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About the Role
This role focuses on the development of DDR memory subsystems for in-vehicle SoCs (R-Car series), a critical area for determining vehicle value in the era of automotive electrification and intelligence. The position involves contributing to specification, microarchitecture design, RTL design, verification, debugging, and performance evaluation, while collaborating with internal and external teams to resolve technical challenges.
Responsibilities
- Engage in the practical development of DDR memory subsystems for in-vehicle SoCs (R-Car series).
- Focus on DDR memory controllers, participating in specification, microarchitecture design, RTL design, verification, debugging, and performance evaluation.
- Design with consideration for SoC-wide consistency, addressing requirements for memory bandwidth, latency, QoS, refresh, low-power control, and error handling.
- Collaborate with related teams (DDR PHY, interconnect, CPU/accelerator, software) to align interface specifications and resolve technical issues.
- Lead the formulation of design policies and technical issue resolution for the assigned area, fostering consensus among stakeholders.
- Handle specification confirmation, constraint organization, integration, and technical issue resolution with external IP vendors when introducing external IPs.
- Work in a global development environment, coordinating with design sites in Japan, India, and Vietnam using English.
Requirements
- Over 5 years of practical experience in digital circuit design or verification for SoCs or IPs, including RTL design, verification, debugging, specification study, and design review.
- Design or verification experience related to memory controllers, memory peripheral circuits, or data transfer control.
- Experience in translating requirements into circuit specifications and verification items by understanding design specifications and technical documents.
- Experience in collaborative problem-solving through technical discussions with internal and external stakeholders.
- Experience in organizing design policies and technical issues within the assigned area and achieving consensus with stakeholders.
- Comfortable reading/writing technical documents in English and communicating with global teams.
Skills
- DDR/LPDDR memory controller design/verification
- On-chip bus (e.g., AXI)
- QoS control
- Cache coherency
- DMA
- Memory performance analysis
- UVM-based verification environment construction
- Formal verification
- Performance model evaluation
- External IP integration
- IP vendor technical issue resolution
- Power-aware design
- Physical design (P&R)
- Automotive SoC development
- Functional safety, quality, and reliability-focused product development
- JEDEC DDR/LPDDR standards
Location
- Japan
Work Type
- Full-time
- Onsite
Experience Level
- 5+ years
Benefits
- Competitive compensation package
- Comprehensive benefits
About the Company
- Renesas is a global company providing embedded semiconductor solutions, aiming to 'Make Our Lives Easier'.
- With over 21,000 engineers and problem solvers in more than 30 countries, Renesas contributes to a safer, healthier, greener, and smarter future through cutting-edge technology development in automotive, industrial, infrastructure, and IoT sectors.
- Renesas' corporate culture is centered around 'TAGIE' (Transparent, Agile, Global, Innovative, Entrepreneurial), representing shared values that guide their work, growth, and pursuit of their Purpose.
- This collaborative spirit and challenging mindset drive industry transformation through semiconductor technology and contribute to people's lives worldwide.