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About the Role

Cornelis Networks is seeking engineers to lead the design and integration of PCIe controllers into next-generation SoCs. The ideal candidate will have deep expertise in PCI Express protocol (Gen4/Gen5/Gen6), integration into high performance ASICs, emulation and post silicon bring-up.

Responsibilities

Own end-to-end integration of PCIe IP into complex ASIC designs.
Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
Debug functional and performance issues at RTL, gate-level, and silicon.
Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
Provide mentorship to junior engineers and help define PCIe subsystem development best practices.
Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms.

Requirements

BS/MS in Electrical Engineering, Computer Engineering, or related field.
10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
Proven experience in silicon bring-up and debug of high-speed interfaces.
Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).
Strong scripting (Python, Perl, TCL) and debugging skills.
Strong verbal and written communication skills.
Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
Exposure to CXL, CCIX, or other cache-coherent interconnects.
Background in data center or AI/ML accelerator architectures.
Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for PCIe subsystem validation.

Skills

PCIe protocol (Gen4/Gen5/Gen6)
ASIC design
Distributed software systems
PCI Express protocol
High performance ASICs
Emulation
Post silicon bring-up
PCIe IP integration
ASIC designs
PCIe subsystems
Performance optimization
PHY tuning
DMA/transaction layer efficiency
System architecture
Microarchitecture
IO and interconnect scalability
Silicon bring-up
Validation
Lab equipment
RTL
Gate-level
Silicon
PCIe specifications
Interoperability testing
Mentorship
High-bandwidth, low-latency connectivity
High-performance compute platforms
Electrical Engineering
Computer Engineering
SoC design
High-speed interfaces
PCIe protocol stack (PHY, MAC, TLP, DLL)
Configuration space
Link training
PCIe verification environments
Power-aware design
PCIe compliance testing
Simulation tools (e.g., VCS, Questa)
Protocol analyzers
Oscilloscopes
Scripting (Python, Perl, TCL)
Debugging
Verbal communication
Written communication
PCIe Gen5/Gen6
Advanced retimer or switch solutions
CXL
CCIX
Cache-coherent interconnects
Data center architectures
AI/ML accelerator architectures
Emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS)

Location

United States

Work Type

Remote
Onsite
Hybrid

Experience Level

Senior
10+ years

Education Level

BS/MS in Electrical Engineering, Computer Engineering, or related field

Salary/Compensations

Competitive compensation package that includes equity, cash, and incentives

Benefits

Health benefits
Retirement benefits
Medical coverage
Dental coverage
Vision coverage
Disability insurance
Life insurance
Dependent care flexible spending account
Accidental injury insurance
Pet insurance
Generous paid holidays
401(k) with company match
Open Time Off (OTO) for regular full-time exempt employees
Sick time
Bonding leave
Pregnancy disability leave

About the Company

Cornelis Networks is building the future of AI and HPC networking with an AI-first approach to silicon and software development.
Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters.
Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale.
Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation.
Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.
We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies.
As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.

Equal Opportunity

Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.