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About the Role

As a senior leader in the central physical design team, you will shape the long-term vision for physical design capabilities and infrastructure, lead RTL-to-GDSII implementation for multiple SoC programs, and provide strategic leadership and technical direction to physical design teams. You will mentor and develop engineering talent, oversee team structure, drive cross-functional collaboration, and manage project schedules and resources.

Responsibilities

Shape the long-term vision for physical design capabilities and infrastructure in alignment with company-wide technology strategy.
Lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS).
Provide strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs.
Mentor and develop engineering talent, fostering a culture of innovation, collaboration, and continuous improvement.
Oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization.
Drive cross-functional collaboration with design teams to influence design decisions and ensure successful project execution.
Navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams.
Drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality.
Manage project schedules, resources, and risk, ensuring alignment with business goals and customer requirements.
Represent the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy.
Collaborate with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies.

Requirements

Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
15+ years of progressive experience in back-end physical design and verification, including significant leadership roles.
Proven track record of leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules.
Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges.
In-depth understanding of current design technologies used in major foundries.
Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure.
In-depth knowledge of modern EDA tools and flows.
Proficient in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness.
Strong communication and collaboration skills, with the ability to influence cross-functional teams and executive stakeholders.
Experience in developing and deploying advanced physical design methodologies and flows.
Familiarity with AI/ML-driven optimization in physical design tools is a plus.
Must be eligible to access export-controlled information as defined under applicable law.
Candidates are not permitted to use AI tools during interviews.

Skills

Physical design
Verification
RTL-to-GDSII implementation
Synthesis
Floorplanning
Power grid design
Place and route
Clock tree synthesis
Timing closure
Power/signal integrity signoff
Physical verification (DRC/LVS)
Automation
Scripting (Makefile, Tcl, Python, Perl)
AI/ML-driven optimization in physical design tools

Experience Level

Senior leader
15+ years of progressive experience

Education Level

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
Master’s degree in Electrical Engineering, Computer Engineering, or a related field
PhD degree in Electrical Engineering, Computer Engineering, or a related field

Salary/Compensations

179,900 - 266,180 USD per annum

Benefits

Eligible to participate in Marvell's bonus and equity plans
New hire equity grant
Annual equity refreshers
Employee stock purchase plan with a 2-year look back
Family support programs
Robust mental health resources
Recognition and service awards

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
Across enterprise, cloud and AI, and carrier architectures, Marvell's innovative technology is enabling new possibilities.
Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models.
Opportunity to work on both the physical design and methodology for future designs of next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.