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About the Role

In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

Responsibilities

Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner.
Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools.
Work with RTL design teams to drive assembly and design closure.
Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.
Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or equivalent professional experience in lieu of a formal degree
Expertise in full-chip & sub-hierarchy integration.
Experience integrating and taping out large designs utilizing a digital design environment.
Good understanding of RTL to GDS flows and methodology.
Good scripting skills in Perl, tcl and Python.
Good understanding of digital logic and computer architecture
Knowledge of Verilog.
Good communication skills and self-discipline contributing in a team environment.
Experience with multi-voltage and low-power design techniques is a plus.
Experience with Cadence Innovus is preferred.
Must be eligible to access export-controlled information as defined under applicable law.
May be subject to an export license review process prior to employment.

Skills

Shell scripting
Python scripting
TCL scripting
Perl scripting
Verilog

Experience Level

3-5 years of related professional experience
2-3 years of experience

Education Level

Bachelor’s degree in Computer Science, Electrical Engineering or related fields
Master’s degree
PhD

Salary/Compensations

112,300 - 166,280, $ per annum

Benefits

Eligible to participate in Marvell's bonus and equity plans
New hire equity grant
Annual equity refreshers
Employee stock purchase plan with a 2-year look back
Family support programs
Robust mental health resources
Recognition and service awards

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.