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About the Role

Join Marvell's custom Processor/ASIC solution team to work on the physical design and methodology for next-generation, high-performance processor chips. This role offers the opportunity to impact data infrastructure and drive innovation in server, 5G/6G, and networking applications.

Responsibilities

• Architect and lead the development of next-generation physical design methodologies and automation flows.
• Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure.
• Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges.
• Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution.
• Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization.
• Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors.
• Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution.

Requirements

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of progressive experience in back-end physical design and verification, including leadership roles.
• Deep understanding of RTL to GDSII flows, including synthesis, place and route, clock tree synthesis, and timing closure.
• Strong expertise in static timing analysis (e.g., PrimeTime, Tempus) and power/signal integrity tools (e.g., Voltus, RedHawk).
• Proficient in scripting languages such as Python, Perl, Tcl, and Makefile for automation and flow development.
• Demonstrated experience in developing and deploying physical design methodologies and flows.
• Strong communication and collaboration skills, with the ability to mentor junior engineers and influence cross-functional teams.
• Experience working with EDA vendors and evaluating new tools and technologies is a plus.
• Must be eligible to access export-controlled information as defined under applicable law.
• Applicants may be subject to an export license review process prior to employment.

Skills

• Physical Design
• Methodology Development
• RTL-to-GDSII Implementation
• Synthesis
• Floorplanning
• Place and Route
• Clock Tree Synthesis
• Timing Closure
• Static Timing Analysis
• PrimeTime
• Tempus
• Power/Signal Integrity Analysis
• Voltus
• RedHawk
• Python
• Perl
• Tcl
• Makefile
• EDA Tools
• Communication
• Collaboration
• Mentoring

Experience Level

• 10+ years of progressive experience
• Leadership roles

Education Level

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
• Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• PhD degree in Electrical Engineering, Computer Engineering, or a related field

Salary/Compensations

• 156,400 - 231,440, $ per annum

Benefits

• Eligibility for Marvell's bonus and equity plans
• New hire equity grant
• Annual equity refreshers
• Employee stock purchase plan with a 2-year look back
• Family support programs
• Robust mental health resources
• Recognition and service awards

About the Company

• Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
• Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
• At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
• For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
• Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models.

Equal Opportunity

• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.