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About the Role

Join Apple's mixed-signal ASIC team to develop sophisticated digital IPs for power conversion and system management ICs. You will craft complex digital IPs for Apple's custom mixed-signal integrated circuits, working with cross-functional teams from concept through mass production. Contribute to building Apple's next-generation products and delivering the 'surprise and delight' in future devices.

Responsibilities

• Deliver complex digital IPs, meeting schedule, area, power, and performance targets.
• Collaborate in developing precise design specifications for digital control blocks.
• Implement physical design ready blocks in System Verilog.
• Collaborate with project leads to track progress and gauge tapeout readiness.
• Work with DV teams to create verification plans.
• Work with silicon validation team in developing lab validation and qualification plans.

Requirements

• Bachelors degree or higher in electrical engineering or computer engineering.
• Familiarity with power estimation tools and techniques.
• Familiarity with digital ASIC development flows and milestones.
• Solid understanding of low power design techniques.
• Experience developing digital IPs for SoCs or mixed signal ICs.
• Proven track record of delivering quality designs on schedule.
• Experience with synthesis and static timing tools.
• Expertise in Clock Domain Crossing design and verification techniques.

Skills

• System Verilog
• Clock Domain Crossing design and verification techniques

Location

• Apple Park

Work Type

• Full-time

Experience Level

• Entry-level to Mid-level

Education Level

• Bachelors degree or higher in electrical engineering or computer engineering

About the Company

• Apple is a global leader in developing custom mixed-signal integrated circuits, with hundreds of millions of chips shipped into existing and future product lines.
• The mixed-signal ASIC team is a close-knit, prolific, and diverse group that values new approaches to deliver creativity, high productivity, and industry-leading results.