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About the Role

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You will lead physical verification closure, debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts.

Responsibilities

• Drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes.
• Lead physical verification closure (DRC, LVS, ERC, etc.).
• Debug issues using standard industry PV tools.
• Collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts.
• Mentor and technically lead in building efficient, manufacturable silicon.
• Learn advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Learn integration and verification strategies for full-chip signoff across advanced process technologies.
• Learn cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Learn leadership and mentoring opportunities in building scalable PV methodologies and automation.

Requirements

• BS or MS in Engineering (Electrical, Electronics, or related field).
• 7–14 years of hands-on experience in CPU/IP/SoC physical verification.
• Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification.
• Solid understanding of advanced node challenges (7nm, 5nm, 3nm) and FinFET design considerations.
• Scripting proficiency (Python, TCL) for automation and flow optimization.
• Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
• Eligibility to access U.S. export-controlled technology.

Skills

• Physical verification
• Tapeout closure
• DRC
• LVS
• ERC
• PERC
• Antenna
• DFM verification
• Calibre
• ICV
• Pegasus
• FC
• Innovus
• Python
• TCL
• ESD planning
• Padring integration
• Bump/RDL strategies
• Reliability analysis
• IR drop
• EM

Location

• Santa Clara, CA
• Austin, TX
• Fort Collins, CO

Work Type

• Hybrid

Experience Level

• Various experience levels
• 7-14 years

Education Level

• BS or MS in Engineering (Electrical, Electronics, or related field)

Salary/Compensations

• $100k - $500k

Benefits

• Highly competitive compensation package

About the Company

• Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.
• Solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
• Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.
• We value collaboration, curiosity, and a commitment to solving hard problems.
• We are growing our team and looking for contributors of all seniorities.

Equal Opportunity

• We are an equal opportunity employer.
• This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.