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About the Role
This role focuses on driving Physical Design (PnR) and Physical Synthesis to optimize Power, Performance, and Area (PPA) for advanced technology nodes. You will work across the synthesis-to-PnR boundary, utilizing leading industry tools to achieve end-to-end PPA optimization.
Responsibilities
- Drive end-to-end PPA optimization by working across the synthesis-to-PnR boundary.
- Perform Physical Synthesis, Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing.
- Handle advanced technology nodes, including node-specific challenges like double/multi-patterning, pin access, cell legalization, and advanced DRC rules.
- Write and tune timing constraints for synthesis, STA, timing closure, and pipelining for performance optimization.
- Focus on PPA activities: area recovery, power reduction, and performance enhancement, balancing trade-offs.
- Manage timing closure for multi-clock domain, multi-corner multi-mode (MCMM) designs.
- Implement low-power designs using UPF, including power gating, multi-voltage domains, and level shifter/isolation cell placement/routing.
- Utilize power optimization techniques across synthesis and PD, such as clock gating, cell sizing, Vt swapping, and buffer/inverter insertion/optimization.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 6+ years of ASIC design, verification, validation, integration, or related work experience.
- 2+ years of experience with architecture and design tools.
- 2+ years of experience with scripting tools and programming languages.
- 2+ years of experience with design verification methods.
- 1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
Skills
- Physical Synthesis
- Place and Route (PnR)
- Physical Design
- Timing/Power Signoff
- Floorplanning
- Clock Tree Synthesis (CTS)
- Routing
- PPA optimization
- Advanced technology nodes
- Double/multi-patterning
- Pin access
- Cell legalization
- Advanced DRC rules
- Timing constraints
- Static Timing Analysis (STA)
- Timing closure
- Pipelining
- Low-power design implementation (UPF)
- Power gating
- Multi-voltage domains
- Level shifter/isolation cell placement/routing
- Power optimization techniques
- Clock gating
- Cell sizing
- Vt swapping
- Buffer/inverter insertion/optimization
- Python/Tcl
- AI Usage
- Version Control
- Configuration Management
- Regression
- PnR tools (Innovus/ICC2)
- Synthesis tools (Fusion Compiler/Genus)
- Static Timing Analysis (PrimeTime/Tempus)
- LEC
- Low Power (LP) signoff tools
- VLSI front-end and back-end design steps
- QoR optimization
- Equivalence Checking
- Computer architecture
- High-speed, low-power processor design
Experience Level
- 5 to 10 years of hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff.
Education Level
- Bachelor's degree in Science, Engineering, or related field
- Master's degree in Science, Engineering, or related field
- PhD in Science, Engineering, or related field
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
Salary/Compensations
- $140,000.00 - $210,000.00
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package
About the Company
- Qualcomm Technologies, Inc. is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process for individuals with disabilities.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
- Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Equal Opportunity
- Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.