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About the Role

Own the top-level RTL design and integration of AMD's mixed-signal power management IP, driving the design through timing closure and tape-out in partnership with physical design and verification teams.

Responsibilities

• Own top-level RTL design and analog macro integration for mixed-signal power management IC
• Partner with analog macro teams on block integration, including bring-up and debug of analog behavioral models in the digital simulation environment
• Author micro-architecture specifications in partnership with Architecture and Firmware
• Act as primary interface between RTL design and the Physical Design / timing closure team
• Create and review timing constraints (SDC), including analog macro boundaries and clock-domain crossings
• Drive timing closure and ECO support through tape-out; manage area, power, and floorplan tradeoffs with PD
• Own RTL signoff before each release to PD: lint, CDC/RDC, synthesis QoR, and connectivity checks
• Partner with the verification team to define and review test plans and coverage goals
• Validate analog behavioral models against analog design intent for functionality and timing, and drive discrepancies to resolution with the Analog team
• Debug block- and system-level simulation failures to root cause
• Support post-silicon bring-up and silicon-to-RTL correlation
• Work across Analog, Firmware, Systems Engineering, and Architecture teams
• Mentor junior engineers and lead design reviews

Requirements

• RTL design in SystemVerilog, with ownership of blocks or subsystems through tape-out
• Hands-on experience with timing constraints (SDC) development and timing closure on production silicon
• Proficiency with synthesis, lint, and CDC/RDC tools and their integration into a design flow
• Strong scripting skills in Python and TCL
• Top-level SOC or chip-level integration ownership on a mixed-signal device
• Integration and debug of analog behavioral models (Verilog-AMS, real-number/wreal modeling) in a digital simulation environment
• Low-power design methodology and UPF-based power intent
• Familiarity with standard control interfaces used in power management (I²C, SPI, APB, SVID/PMBus)
• Post-silicon bring-up and debug experience, including silicon-to-RTL correlation
• This role is not eligible for visa sponsorship.

Skills

• Digital design
• Mixed-signal integration
• Silicon validation
• Communication skills
• Analytical skills
• Problem-solving skills
• SystemVerilog
• Timing constraints (SDC)
• Timing closure
• Synthesis
• Lint
• CDC/RDC
• Python scripting
• TCL scripting
• Verilog-AMS
• Real-number modeling
• wreal modeling
• Low-power design methodology
• UPF
• I²C
• SPI
• APB
• SVID/PMBus

Education Level

• Bachelors or master's in electrical/computer engineering

Benefits

• AMD benefits at a glance.

About the Company

• AMD believes technology can change lives for the better.
• AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI.
• Every role at AMD contributes to something bigger — technology that moves the world forward.

Equal Opportunity

• AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
• We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.