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About the Role

Investigate and root-cause failures in advanced custom digital megacells (SRAM memories, on-chip sensors, custom data paths) used in high-performance, low-power SoCs. Bridge the gap between electrical debug and physical failure analysis, working at the frontier of silicon investigation. Play a central role in ensuring the quality and reliability of state-of-the-art ASICs.

Responsibilities

• Systematically uncover the root cause of complex silicon failures, from electrical characterization to physical analysis.
• Apply deep engineering fundamentals and cutting-edge failure analysis techniques.
• Collaborate across circuit design, process engineering, DFT, and failure analysis teams.
• Conduct structured experiments during silicon debug.
• Gather and analyze large datasets.
• Utilize scripting to support efficient handling of debug data.
• Plan failure analysis strategies based on electrical debug data.
• Interpret failure analysis results in the context of circuit topology and failure electrical signatures.

Requirements

• A minimum of a bachelor's degree in a relevant field.
• A minimum of 10 years of relevant industry experience.
• Proficiency in scripting languages (Python, Perl, or others).
• Proficiency in CAD automation tools.
• Knowledge of industry-standard circuit design and simulation tools.

Skills

• Silicon debug
• Electrical characterization
• Physical analysis
• Failure analysis
• SRAM circuits
• Custom circuit design
• Low-voltage / low-power custom circuit design or debug
• Deep-submicron device physics
• Leakage mechanisms
• Technology interactions with device behavior
• Device matching
• Device noise sources (1/f, thermal)
• Extrinsic noise sources (supply noise, jitter)
• Electrical failure analysis (eFA) techniques
• Physical failure analysis (pFA) workflows
• Dynamic Lock-in Thermography (DLS)
• Lock-in Thermography (LIT)
• Nanoprobe techniques
• Photon emission maps
• OBIRCH
• Thermal maps
• TEM/SEM imagery
• Python
• Perl

Location

• On-site

Work Type

• Full-time

Experience Level

• 10+ years of relevant industry experience

Education Level

• Bachelor's degree in a relevant field

About the Company

• We have an extraordinary opportunity for Silicon Debug Engineers to investigate and root-cause failures in advanced custom digital megacells (SRAM memories, on-chip sensors, custom data paths) used in high-performance, low-power SoCs.
• Join us, and you'll play a central role in ensuring the silicon we build is everything it needs to be.