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About the Role

Join the Logic Technology Development (LTD) organization as a Principal Engineer to lead Intel's foundry revolution. You will serve as a strategic technical architect and executive partner, guiding critical customers through the product development lifecycle. This role involves orchestrating multidisciplinary strategies, defining roadmaps, and providing executive technical leadership in the AI innovation era.

Responsibilities

Establish the overarching yield strategy and governance framework for the foundry product lifecycle.
Define and steer long-term yield/performance goals, technology features, and roadmaps for foundry customer silicon.
Lead strategic initiatives to identify and eliminate systematic and parametric yield detractors.
Oversee the development of advanced predictive models for parametric and defective yield loss.
Define standards for correlating inline process metrics with end-of-line yield and performance.
Direct the execution of New Product Introduction (NPI), overseeing wafer lot progress, skew split strategy, and targeting.
Lead the analysis of device performance and variability for logic, SRAM, and emerging device types.
Architect complex Design of Experiments (DOE) and skew split plans.
Ensure organizational adherence to critical customer technology metrics.
Drive the vision for high-quality Process Design Kits (PDKs).
Oversee Sil2Sim correlation frameworks and layout effect assessments.
Chair or provide executive guidance to the Waiver Review Board (WRB).
Lead the strategy for intellectual property (IP) design activities.
Serve as the primary executive process expert and strategic interface between external foundry customers and internal leadership.
Deliver high-level technical readouts and strategic health reports on process development.
Own the LTD customer technology deliverables and the product Plan of Record (POR).
Act as the final point of resolution for critical technical blockers.
Define and institutionalize best-in-class foundry customer service practices and IP/data management systems.
Drive the transformation of operational systems and methodologies.
Lead the central TD factory teams in auditing and improving product yield/performance commits.
Architect the integration between development, assembly, and test teams.

Requirements

Master's Degree with 13+ years of experience OR PhD Degree with 10+ years of industry experience in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline.
Minimum of 13 years (Master's) or 10 years (PhD) of related work experience in Semiconductor integration, device engineering, or yield engineering.
10+ years of direct semiconductor yield and performance analysis and strategic engineering leadership.
Proven track record in yield pareto construction, modeling, projection, and the development of long-term yield roadmaps.
Proven track record in process integration, device engineering, performance projection, and the development of long-term performance roadmaps.
Extensive experience leading a foundry team or managing high-level foundry customer collaborations.
Expertise in interpreting complex product data (inline, e-test, and SORT) to drive organization-wide solutions.
Deep knowledge of inline inspection methods and SORT programs.
Deep experience collaborating with fabless design houses on product development cycles.
Proven history of executive-level customer service and strong customer orientation in a foundry environment.
Must consent to and pass an extended Background Investigation.

Skills

Yield Engineering
Performance Optimization
Strategic Yield Governance
Roadmap Architecture
Systemic Loss Mitigation
Predictive Modeling
AI/ML
Metric Correlation Frameworks
NPI Execution
Device Performance Analysis
Experimental Design (DOE)
Technology Compliance
PDK Management
Simulation Standards
Governance and Risk Management
IP Ecosystem Development
Customer Management
Foundry Ecosystem Design
Operational Excellence
Continuous Improvement (CIP)

Location

US, Oregon, Hillsboro
US, Arizona, Phoenix
US, California, Folsom
US, California, Santa Clara
US, Texas, Austin

Work Type

Hybrid

Experience Level

Experienced Hire
Principal Engineer

Education Level

Master's Degree
PhD Degree

Salary/Compensations

$220,920.00-311,890.00 USD

Benefits

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation

About the Company

Intel is the world's largest chip manufacturer and a global leader in innovation and new technology.
Intel strives to make every facet of semiconductor manufacturing state-of-the-art.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network focused on utilizing Moore's Law.
Intel fosters a collaborative, supportive, and exciting environment.
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.