Design Architect Analog IC Designer at Cadence Design Systems | CA | Rezi

Design Architect Analog IC Designer at Cadence Design Systems

Design Architect Analog IC Designer

Cadence Design Systems · CA

4 days ago

Design Architect Analog IC Designer

Cadence Design Systems · CA

5 days ago
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About the Role

The Design Architect Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. This role contributes to the design of long-reach SerDes.

Responsibilities

  • Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.
  • Contribute to the design of long-reach SerDes.

Requirements

  • Minimum of 10 years of experience in the development of CMOS SerDes or high-speed I/O IC.
  • Thorough understanding of jitter and signal equalization techniques.
  • Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators.
  • Excellent problem-solving skills.
  • Good communication skills.
  • Ability to work cooperatively in a team environment.
  • Working knowledge of a set of common SerDes standards and their electrical requirements is a plus.
  • Proficiency in using CAD tools for circuit simulation, and post-layout verification.
  • Proficiency with layout entry is a plus.
  • Cadence tool experience.
  • Lab test experience.
  • Design experience at ≥16Gbps.
  • Design experience in ≤16nm technologies.

Skills

  • Analog/mixed signal IC circuit design
  • SerDes design
  • Jitter understanding
  • Signal equalization techniques
  • Driver design
  • Receiver design
  • Serializer design
  • Deserializer design
  • Phase Interpolator design
  • Low jitter PLL design
  • High Speed Clock Distribution design
  • ADC design
  • DAC design
  • Bias circuit design
  • Bandgap circuit design
  • Voltage Regulator design
  • Problem-solving
  • Communication
  • Teamwork
  • CAD tools for circuit simulation
  • Post-layout verification
  • Layout entry
  • Cadence tools
  • Lab testing
  • Design at ≥16Gbps
  • Design in ≤16nm technologies

Experience Level

  • Minimum of 10 years of experience

Education Level

  • MS or PhD in EE

About the Company

  • At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • We’re doing work that matters. Help us solve what others can’t.

Equal Opportunity

  • We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.