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About the Role

As an AI Compiler Engineer on the Renesas HPC team, you will drive compiler and code generation technologies for Renesas next-generation automotive System-on-Chip platforms. Your work will optimize AI workloads for safe and power-efficient execution on Renesas hardware, bridging compiler development, AI model optimization, and hardware-software co-design.

Responsibilities

• Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration.
• Design and implement graph-level optimizations (operator fusion, quantization-aware rewrites, memory-aware scheduling, partitioning).
• Drive performance optimization for target NPUs, including tiling, tensor layout, and multi-core execution strategies.
• Partner with SoC and AI accelerator architects to influence hardware features through compiler insights.
• Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon-correlated models.
• Ensure compiler outputs meet automotive requirements (real-time behavior, determinism, quality expectations).
• Mentor senior engineers and set technical direction without people-management responsibilities.

Requirements

• MS/PhD (or equivalent experience) in Computer Science, EE, or related field.
• Deep experience building AI compilers, accelerator backends, or graph optimization frameworks.
• Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators.
• Experience with MLIR, LLVM, TVM-like systems, or proprietary compiler IRs.
• Excellent C/C++ and Python skills.
• Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models).
• Strong communication skills are required.
• Agile development experience in Scrum team (Product Owner or Scrum Master).
• Experience with automotive or safety-critical systems.
• Background in heterogeneous SoCs (CPU/GPU/DSP/NPU).
• Performance modeling or hardware–software co-design experience.

Skills

• Compiler architecture
• Graph optimization
• Code generation
• Runtime integration
• Operator fusion
• Quantization-aware rewrites
• Memory-aware scheduling
• Partitioning
• Performance optimization
• NPU optimization
• Tiling
• Tensor layout
• Multi-core execution
• Hardware-software co-design
• MLIR
• LLVM
• TVM
• C++
• Python
• AI inference workloads
• CNNs
• Transformers
• Perception models
• Generative models
• Automotive systems
• Safety-critical systems
• Heterogeneous SoCs
• Performance modeling

Location

• Remote Work Available: No

Work Type

• Regular (PERM)

Education Level

• MS/PhD (or equivalent experience) in Computer Science, EE, or related field

Benefits

• Competitive compensation
• Comprehensive benefits package

About the Company

• Renesas is a global company providing embedded semiconductor solutions, aiming to 'Make Our Lives Easier'. With over 21,000 engineers and problem-solvers in more than 30 countries, we contribute to developing world-leading technologies in automotive, industrial, infrastructure, and IoT fields, fostering a safer, healthier, environmentally friendly, and smarter future.
• Our corporate culture is centered around TAGIE (Transparent, Agile, Global, Innovative, Entrepreneurial), representing our shared values that guide our work, growth, and pursuit of our Purpose. This collaborative spirit and challenging mindset enable us to transform industries through semiconductor technology and contribute to people's lives worldwide.
• We offer competitive compensation and a comprehensive benefits package. Details will be provided during the selection process.
• Join us in creating the future. We look forward to your application.