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About the Role

We are seeking a Principal Package Design Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architecture, assembly processes, thermal and mechanical reliability, and cross-functional collaboration.

Responsibilities

• Lead the design, development, and qualification of advanced semiconductor packaging solutions, including Flip-chip, Chip Embedding, Wafer-level packaging (WLP/FOWLP), Panel-level packaging (laminate, molding), 2.5D/3D packaging, System-in-package (SiP), Ball grid array (BGA/CSP), Wafer-to-wafer and die-to-wafer heterogeneous bonding.
• Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements with hands-on, deep simulation expertise.
• Drive package technology and OSAT selection and development for new product introductions (NPI).
• Work closely with IC design, product definers, substrate, board, thermal, reliability, applications, and manufacturing teams to ensure package compatibility and performance.
• Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Perform and guide others on simulations and analysis related to signal integrity/power integrity, thermal performance, mechanical stress/warpage, and design for manufacturability (DFM).
• Develop assembly flows and process requirements for OSATs and manufacturing partners.
• Lead package qualification activities, including DOE planning, failure analysis, and reliability testing.
• Resolve packaging-related issues and challenges during NPI prototype builds, qualification, and production ramp.
• Collaborate with suppliers and internal/external manufacturing partners on process improvements, material evaluation, and yield optimization.
• Create and maintain package specifications, design rules, process documentation, and technical reports.
• Mentor junior engineers and provide technical leadership across packaging initiatives.

Requirements

• MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field.
• 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration.
• Strong hands-on knowledge of advanced packaging technologies, materials, assembly processes, and application system integration as they apply to AI infrastructure and data center power management.
• Deep understanding of thermal, mechanical, and reliability interactions in package design.
• Extensive, hands-on model setup, simulations, and analysis.
• Strong background in CAD and simulation tools.
• Experience with package reliability testing and qualification standards.
• Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
• Proven ability to troubleshoot packaging failures, drive root cause/corrective action, and demonstrate strong project leadership and cross-functional communication skills.
• Master’s or PhD in a relevant engineering discipline.
• Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETs, Power Modules, Intelligent Power Modules, and their applications in consumer, industrial, automotive, and high-performance computing markets.
• Experience with power products in high-performance computing, AI/ML hardware, or mobile products.
• Hands-on experience with tools for package design and simulation such as Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP / Minitab.
• Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods.
• Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging.

Skills

• Advanced package concept engineering and design
• Materials selection and development
• Thermal and mechanical simulations and analysis
• Failure analysis & reliability engineering
• Design for Manufacturability (DFM/DFX)
• Process development & supplier collaboration
• Technical leadership & problem-solving

Location

• San Jose, CA
• Austin, TX

Work Type

• Hybrid

Experience Level

• Principal

Education Level

• MSc
• PhD

Benefits

• Competitive benefits package

About the Company

• Renesas is the engine behind a "safer, smarter, and more sustainable" future.
• Headquartered locally in the heart of San Jose, our Silicon Valley team is at the forefront of innovation in Automotive, Industrial, Infrastructure, and IoT technologies.
• By blending cutting-edge embedded processing with world-class analog and power expertise, we develop "Winning Combinations" that power billions of intelligent devices globally.
• Joining our San Jose office means joining a collaborative, forward-thinking environment where your work directly impacts the next generation of AI-driven infrastructure and green energy solutions.
• Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier.
• With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
• At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together.
• This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

Equal Opportunity

• Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law.