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About the Role

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Our patented technology uses 100x less energy than state-of-the-art ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible, enabling continuous AI/ML operation on a AA battery for 5-10 years. Our platform's unprecedented efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution.

Responsibilities

Own the program end-to-end — from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release.
Act as the operational center of the program: build and defend the schedule, drive the critical path, surface risk early, and facilitate tradeoff conversations.
Work daily with architecture, RTL design, DV/emulation, DFT, physical design, package, firmware, and the foundry/IP vendor ecosystem.
Own the silicon schedule from architecture freeze through tapeout, bring-up, and production, informed by customer requirements and internal functional leads.
Drive the weekly execution cadence, including program reviews, design reviews, and tapeout readiness, maintaining a single source of truth for status, dependencies, and decisions.
Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, IP, package, and software.
Manage dependency chains such as IP delivery, PDK/library releases, EDA versions, and emulation capacity.
Run the tapeout checklist and signoff matrix, holding owners to closure criteria.
Collaborate with supply chain/logistics for IP acquisition, silicon arrival, ATE/loadboard readiness, lab scheduling, bug triage, and ECO/respin decision support.
Surface risk early with mitigation options and quantified schedule impact.
Facilitate PPA, schedule, and scope tradeoffs, documenting decisions, owners, and rationale.
Interface with foundry, OSAT, IP, and EDA partners on deliverables, technology file releases, mask slots, and escalations.
Support export control/ECCN compliance with legal and operations.
Deliver crisp executive reporting on program status, risks, and required decisions.
Track resource allocation and NRE/mask/license/prototype budgets against program needs.

Requirements

B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA a plus.
7+ years in semiconductor/hardware engineering or program management.
At least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up.
Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation.
Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping.
Track record of influencing without authority, earning technical credibility to push senior engineers on commitments and dates.
Strong written and verbal communication skills.
Hands-on experience with program tooling: Jira, Confluence, MS Project/Smartsheet.
Familiarity with the Synopsys/Cadence/Siemens EDA ecosystem.
Prior hands-on engineering experience in design, DV, or physical design before moving to program management.
Experience on advanced or FinFET nodes (16/12/7nm or more advanced) and direct foundry engagement (TSMC preferred).
Familiarity with AI/ML accelerators, dataflow or novel compute architectures.
Experience managing emulation/FPGA prototyping programs and pre-silicon software enablement timelines.
Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination.
Experience with EVK/reference board programs and customer/FAE enablement schedules.
Familiarity with quality and compliance frameworks relevant to the target market (automotive, industrial, or security certifications).

Skills

RTL
Functional verification and coverage closure
DFT
Synthesis
PnR
STA
Physical signoff (DRC/LVS/IR/EM)
GDSII handoff
Post-silicon validation
Critical path analysis
Dependency mapping
Jira
Confluence
MS Project/Smartsheet
Synopsys/Cadence/Siemens EDA ecosystem
AI/ML accelerators
Dataflow or novel compute architectures
Emulation/FPGA prototyping
Pre-silicon software enablement
Package/board co-design
FC-BGA
WLCSP
OSAT coordination
EVK/reference board programs
Customer/FAE enablement
Quality and compliance frameworks

Experience Level

7+ years in semiconductor/hardware engineering or program management
At least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up

Education Level

B.S. in Electrical/Computer Engineering, Computer Science, or equivalent
M.S. or MBA a plus

Salary/Compensations

$200,000 to $240,000

Benefits

Bonus
Meaningful equity
Comprehensive benefits
401K match
Company-paid benefits
Equity program
Paid parental leave
Flexibility

About the Company

Efficient is developing the world’s most energy-efficient general-purpose computer processor.
Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks.
This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years.
Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution.
We are committed to personal and professional development and strive to grow together as people and as a company.