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About the Role

Qualcomm is seeking an experienced PCIe Subsystem Architect to define and deliver high-performance I/O architectures for next-generation AI products in the datacenter. The role involves defining subsystem architecture and driving requirements from the accelerator card and server level through full-rack scale-up and scale-out deployments.

Responsibilities

In-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
Strong understanding of PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
Strong understanding of PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
Experience with PCIe error containment and recovery mechanisms such as Advanced Error Reporting (AER), Downstream Port Containment (DPC), Configuration Request Retry Status (CRS), Function Level Reset (FLR), and reset separation.
Experience with I/O virtualization and isolation technologies such as SR-IOV, SIOV, PF/VF isolation, and related software-visible requirements.
Strong understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
Good knowledge of scale-up and scale-out architectures, including PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment considerations.
Ability to work effectively in a high-caliber, international, multi-site engineering team.
Good understanding of PCIe integrity, security, and confidential-compute features such as IDE, DOE/SPDM, TDISP, SR-IOV, and SIOV.
Strong familiarity with PCIe CEM standards, add-in card deployment constraints, retimers, signal-integrity considerations, and system-level validation flows.
Good understanding of emerging AI interconnect standards and ecosystems such as UCIe, UALink/UAL, and UEC.
Good understanding of PCIe firmware, BIOS/UEFI, operating-system, driver, and system-software requirements.
Good understanding of high-speed SerDes and PHY technologies, including PCIe PHY, Ethernet PHY, PAM4 signaling, and power/performance tradeoffs.
Good knowledge of server SoC architectures with emphasis on security, RAS, virtualization, IOMMU/SMMU, DMA, address translation, and telemetry.
Ability to engage with customers, product management, systems teams, and cross-functional architecture stakeholders to gather requirements and drive technical alignment.
Excellent written and verbal communication skills, with the ability to create architecture specifications, requirement documents, and executive-level technical summaries.

Requirements

Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 10+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 8+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 6+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
3+ years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.

Skills

PCIe
CXL
UCIe
Non-Volatile Memory Express (NVMe)
Ethernet
Datacenter connectivity standards
High-speed interfaces
ASIC design
ASIC verification
ASIC validation
ASIC integration
ARM ordering behavior
DMA flows
High-speed serial interface behavior
PCIe Gen6/Gen7
FLIT mode
PAM4 signaling
Link training
Error handling
System-level tradeoffs
PCIe error containment
PCIe error recovery
Advanced Error Reporting (AER)
Downstream Port Containment (DPC)
Configuration Request Retry Status (CRS)
Function Level Reset (FLR)
Reset separation
I/O virtualization
I/O isolation
SR-IOV
SIOV
PF/VF isolation
RAS
Telemetry
Reliability
Security
Scale-up architectures
Scale-out architectures
PCIe switch fabrics
NIC connectivity
Host-to-accelerator orchestration
Rack-level deployment
PCIe integrity
Confidential-compute features
IDE
DOE/SPDM
TDISP
PCIe CEM standards
Add-in card deployment
Retimers
Signal-integrity
System-level validation
AI interconnect standards
UALink/UAL
UEC
PCIe firmware
BIOS/UEFI
Operating-system
Driver
System-software
High-speed SerDes
PHY technologies
PCIe PHY
Ethernet PHY
Power/performance tradeoffs
Server SoC architectures
IOMMU/SMMU
Address translation
Customer engagement
Product management engagement
Systems teams engagement
Cross-functional architecture stakeholder engagement
Architecture specifications
Requirement documents
Executive-level technical summaries
Software Engineering
Electrical Engineering
Systems Engineering

Experience Level

6+ years
5+ years
4+ years
10+ years
8+ years
6+ years
3+ years

Education Level

Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field
Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field
Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field
PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related field

Salary/Compensations

$164,000.00 - $264,500.00

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package

About the Company

Qualcomm Technologies, Inc. is a global leader in wireless technology innovation, designing and manufacturing semiconductors and providing the software, hardware and services that power the mobile ecosystem and beyond.

Equal Opportunity

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.