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About the Role
You will lead and drive physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced technology nodes. This role requires strong technical leadership to synthesize ambiguous requirements, drive execution across cross-functional teams, and deliver high-quality silicon meeting aggressive power, performance, and area (PPA) targets.
Responsibilities
- Lead and execute end-to-end Physical Design flow for SoC and retimer ASICs, including Floorplanning, Clock Tree Synthesis (CTS), Placement & Routing, Power Delivery Network (PDN), and Timing analysis and closure
- Plan and implement full-chip or hierarchical designs, including full-reticle-scale integration
- Drive timing closure across all corners and modes (MMMC), including SI-aware optimization
- Perform and review physical verification checks: DRC, LVS, Design-for-manufacturability (DFM), Design-for-yield (DFY)
- Collaborate with cross-functional engineering teams (front-end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness
- Lead integration of high-speed SerDes macros and mixed-signal IP, ensuring robust floorplan and signal integrity alignment
- Drive IR/EM closure, power optimization, and congestion mitigation for large die designs
- Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts
- Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions
- Develop and improve physical design methodologies and flows to enhance efficiency and scalability
Requirements
- Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR Bachelor’s degree and 4+ years of progressive experience in ASIC Physical Design or related domain
- Strong experience with end-to-end ASIC Physical Design flow
- Strong experience with timing closure and signoff methodologies
- Strong experience with physical verification flows
- Hands-on expertise in industry-standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2)
- Solid understanding of power delivery and reliability (IR/EM)
- Solid understanding of clocking architectures and CTS
- Solid understanding of large-scale SoC integration challenges
- Proven ability to lead complex PD execution in high-pressure tapeout environments
- Strong analytical and problem-solving skills with attention to detail
- Ability to synthesize ambiguous or conflicting requirements into execution plans
- Effective collaboration across global, cross-functional engineering teams
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Skills
- ASIC Physical Design
- Timing closure
- Signoff methodologies
- Physical verification
- Cadence Innovus
- Synopsys ICC2
- Power delivery
- Power reliability (IR/EM)
- Clocking architectures
- CTS
- SoC integration
- High-speed SerDes
- Retimer designs
- PAM4-class signaling
- Full-reticle SoC implementation
- Multi-die / chiplet / advanced packaging architectures
- Data center ASICs
- Networking ASICs
- Optical connectivity ASICs
- Python scripting
- Tcl scripting
Experience Level
- 3+ years of experience
- 4+ years of progressive experience
- 4+ years of ASIC design, verification, validation, integration, or related work experience.
- 3+ years of ASIC design, verification, validation, integration, or related work experience.
- 2+ years of ASIC design, verification, validation, integration, or related work experience.
Education Level
- Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Bachelor’s degree
- Master's degree in Science, Engineering, or related field
- Bachelor's degree in Science, Engineering, or related field
- PhD in Science, Engineering, or related field
Salary/Compensations
- $124,200.00 - $174,200.00
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package
About the Company
- As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.
Equal Opportunity
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process.
- Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
- Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.