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About the Role

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Our patented technology uses 100x less energy than state-of-the-art processors and enables perpetual, pervasive intelligence. This role involves end-to-end ownership of SOC -top for next-generation SoCs, driving the full chip from block integration through physical closure to tapeout-ready GDS in state-of-the-art finfet technologies. This is an opportunity to influence products from development to scaled production.

Responsibilities

Full-chip integration: floorplanning, power planning, macro/hard-IP placement, and block partitioning at the top level, ensuring convergence across all hierarchical blocks
Timing closure: full-chip STA across all corners/modes (setup, hold, OCV, multi-mode multi-corner), including cross-boundary timing and chip-level constraint (SDC) ownership
Power: full-chip power planning, PDN design/analysis (IR drop, EM), rail architecture, and coordination on power-gating strategy with block owners
Physical verification: DRC/LVS/antenna closure at the top level, seal ring integration, and coordination of ECO cycles across blocks
Signal integrity & noise: crosstalk, di/dt, and chip-level noise closure, especially around high-speed IO and PLL/analog boundaries
Clock & reset architecture: top-level clock tree strategy across domains, including CTS coordination with block owners
DFT integration: chip-level scan stitching, MBIST/JTAG integration, and coordination with DFT lead on ATPG/test coverage closure at full-chip level
Package/IO co-design: bump/ball map coordination, IO ring planning, and package-aware floorplanning
Tapeout readiness: sign-off checklist ownership (timing, power, physical, reliability) and final GDS handoff
Cross-team coordination: single point of contact between block-level PD owners, DV, DFT, package engineering, and architecture on all convergence-related tradeoffs and schedule risk
Technical leadership: mentor block-level PD engineers on convergence best practices; set methodology and flow standards for chip-top closure across the program.

Requirements

Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level
Deep hands-on experience with advanced nodes
Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)
Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map) is a plus
Demonstrated ability to lead technically without direct reports — driving alignment across multiple engineers and teams on convergence decisions
Comfortable operating with significant ownership and ambiguity in a small, fast-moving team
Experience with non-standard/novel architectures (dataflow, tiled, NoC-based) is a plus but not required
Excellent scripting skills in TCL, shell and python.

Skills

Innovus (or ICC2)
Tempus/PrimeTime
RedHawk
Calibre
TCL
shell
python
computer architecture
physical design
ASIC implementation
full chip sign off convergence
circuit design
device physics
deep sub-micron technology
physical design flow
analog or mixed-signal macro integration

Experience Level

5+ years of industry experience (Master's)
3+ years of industry experience (PhD)
8-12+ years of physical design experience

Education Level

Master's degree in Electrical Engineering
PhD in Electrical Engineering

Salary/Compensations

$200,000 to $250,000

Benefits

Meaningful equity
Comprehensive benefits
401K match
Company-paid benefits
Equity program
Paid parental leave
Flexibility

About the Company

Efficient is developing the world’s most energy-efficient general-purpose computer processor.
Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks.
This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years.
Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution.
This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production.
Join our team and help us shape the future of computing at the edge and beyond!