Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

About the Role

The Semi & Custom IP team develops advanced custom SRAM, Register File (RF), and cache memory subsystem IP for next-generation AI accelerators, cloud infrastructure, and custom silicon platforms powering Microsoft’s future AI services and datacenter offerings. We are looking for a Senior Memory Layout Design Engineer to join the custom memory team and drive physical implementation, verification, integration, and delivery of advanced SRAM and RF memory IP supporting Microsoft’s AI silicon roadmap.

Responsibilities

Drive physical implementation of custom SRAM, Register File (RF), cache, and memory layouts in advanced process technologies, including floorplanning, hierarchy development, placement, routing, and physical integration.
Collaborate with circuit design, architecture, physical design, CAD, foundry, and SoC teams to optimize memory IP for power, performance, area (PPA), reliability, manufacturability, and integration readiness.
Perform physical verification and signoff activities including DRC, LVS, ERC, antenna, density, EMIR, reliability analysis, debug, and closure support.
Deliver production-ready memory IP collateral, including GDS/OASIS, LEF abstracts, integration views, documentation, and signoff packages for SoC integration.
Develop and improve custom memory layout methodologies, design-rule adoption, automation flows, and productivity solutions using SKILL, TCL, or similar scripting languages.
Partner with internal engineers, contractors, and external layout teams to review deliverables, resolve technical issues, and support execution to program milestones.
Identify technical risks, communicate status and tradeoffs clearly, and support multiple custom memory programs across advanced technology nodes with high-quality execution.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements.
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Must provide proof of citizenship or US residency for assessment of eligibility to access export-controlled information.
Citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Skills

5+ years of custom memory layout experience including SRAMs, Register Files, cache structures, embedded memories, or high-density memory architectures.
Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.
Experience with DRC, LVS, ERC, antenna, and physical signoff verification on advanced-node designs.
Experience with FinFET and/or Gate-All-Around process technologies.
Experience collaborating with circuit design teams to optimize memory IP for power, performance, and area.
Experience owning or contributing to custom memory IP deliveries from specification through tapeout, including SRAM, Register File (RF), cache, or related embedded memory architectures.
Strong understanding of SRAM and RF architecture fundamentals, including bitcell integration, row/column peripheral circuitry, assist circuitry, redundancy implementation, and layout tradeoffs.
Experience supporting memory integration through LEF/abstract generation, timing or physical collateral development, signoff documentation, and SoC integration readiness.
Experience with EMIR analysis and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools.
Strong automation and scripting skills using Python, SKILL, TCL, Perl, or similar languages to improve layout productivity and quality.
Experience with advanced technology nodes such as 5nm, 3nm, or beyond, and familiarity with analog/mixed-signal layout considerations.
Experience working with geographically distributed teams, contractors, vendors, or design-service partners to deliver layout milestones.

Location

U.S.

Work Type

Full-time

Experience Level

Senior

Education Level

Doctorate
Master's Degree
Bachelor's Degree

Salary/Compensations

USD $119,800 - $234,700 per year (U.S. national range)
USD $160,200 - $261,000 per year (San Francisco Bay area and New York City metropolitan area)

Benefits

Certain roles may be eligible for benefits and other compensation.

About the Company

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s Intelligent Cloud mission.
SCHIE delivers core infrastructure and foundational technologies supporting Azure, Microsoft 365, Teams, Xbox, and next-generation AI platforms at hyperscale, with a focus on high-quality, efficient, and trusted cloud hardware solutions.

Equal Opportunity

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.