Memory Circuit Design Engineer at Intel Corporation | Austin | Rezi

Memory Circuit Design Engineer at Intel Corporation

Memory Circuit Design Engineer

Intel Corporation · Austin

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Memory Circuit Design Engineer

Intel Corporation · Austin

an hour ago
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About the Role

The CPU Circuit Technology team is seeking a Memory Circuit Design Engineer to design, develop, and build full-custom and compiler-based SRAMs, Large Signal Arrays, ROMs, custom memories, digital circuits, and Caches for Intel CPUs and SOCs. You will collaborate with domain experts to deliver industry-leading memory technology and drive circuit innovations for next-generation high-performance, high-density, low-power embedded memory designs on advanced CMOS process technologies.

Responsibilities

  • Technical readiness, memory circuit design, characterization and simulations.
  • Cache design, critical path simulations and design custom blocks.
  • Memory path-finding activities and power, performance and area (PPA) optimization.
  • Memory bit-cell and complex periphery IC design and automation.
  • Memory array/IP design, memory circuit innovation.
  • Methodology definition tasks as well as executing to project schedules.

Requirements

  • Bachelor's degree with 8+ years of experience; or master's degree with 6+ years of experience; or PhD with 4+ years of experience in Electrical Engineering, Computer Engineering, Computer Science or a STEM-related field.
  • 3+ years of experience in CMOS circuit design, digital logic optimizations, and circuit trade-offs for power, performance, and area.
  • 3+ years of expertise in SRAM and Cache design.
  • Experience in low-power implementation techniques and memory design.
  • Familiarity with circuit and layout trade-offs for optimized design.
  • Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis.
  • Strong analytical and problem-solving skills, with the ability to prioritize tasks and work in dynamic environments.

Skills

  • CMOS circuit design
  • Digital logic optimizations
  • Circuit trade-offs for power, performance, and area (PPA)
  • SRAM design
  • Cache design
  • Low-power implementation techniques
  • Memory design
  • Circuit and layout trade-offs
  • EBB design tools, flows and methodologies
  • Signal integrity analysis
  • Analytical skills
  • Problem-solving skills

Location

  • US, Texas, Austin

Work Type

  • Hybrid

Experience Level

  • Experienced Hire

Education Level

  • Bachelor's degree
  • Master's degree
  • PhD

Salary/Compensations

  • $190,610.00-269,100.00 USD

Benefits

  • Competitive pay
  • Stock bonuses
  • Health benefits
  • Retirement benefits
  • Vacation benefits

About the Company

  • Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Equal Opportunity

  • All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.