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Focus on circuit design for memory, I/O (Input/Output), and Standard Cells within the Library Group, a part of the Central Engineering Group.

Understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules, and other technical requirements for quality layout.
Schedule time-line & layout floor-planning.
Complete quality layout and verification within planned schedule.
Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team.
Lead or train a team of junior engineers.
Lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
Manage projects effectively.

Minimum of 3 to 4 years of experience in layout.
Strong layout knowledge in submicron process (e.g., 16nm, 7nm, 5nm, 3nm, 2nm, 1.4nm).
Experienced in digital (standard cell, memory, I/O) layout.
Experienced in analog layout is a plus.
Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
Good experience in Floor-planning, hierarchy layout and chip integration.
Knowledge of Script Programming and SKILL Programming would be a plus.
Good knowledge on memory layout topology.
Experience in memory compiler will be a plus.
Self-reliant, with ability to work independently as well as a team.
Good leadership quality on project management.

We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.
We will also consider qualified applicants with arrest and conviction records consistent with local law.

Layout Engineer at Broadcom

Layout Engineer