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About the Role

Opportunity to work on both the physical design and methodology for future designs of next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

Responsibilities

• Responsible for the physical implementation of complex integrated circuits (ICs).
• Work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
• Engage with diverse engineering challenges within a collaborative and innovative environment.
• Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner.
• Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools.
• Work with RTL design teams to drive assembly and design closure.
• Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.
• Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

Requirements

• Backend physical design and physical verification.
• Physical Design Methodology and Flow Development.
• RTL to GDS flows implementation and methodology.
• Scripting skills in Perl, Tcl, and Python.
• Signoff design rule checking using Design Rule Manual (DRM) for advanced nodes.
• Verilog.
• Multi-voltage and low-power design techniques.
• Cadence Innovus tool.
• Synopsys Fusion Compiler tool.
• Project support for integrating and taping out large designs utilizing a digital design environment.
• Project support for Synthesis flow including both Cadence Genus and Synopsys Fusioncompiler.

Skills

• Shell scripting
• Python scripting
• TCL scripting
• Perl scripting
• Verilog
• Cadence Innovus
• Synopsys Fusion Compiler
• Cadence Genus

Location

• Remote

Work Type

• Full-time

Experience Level

• 3 years of experience

Education Level

• Master’s or foreign equivalent degree in Computer Science, Electrical Engineering, or a related field

Salary/Compensations

• $155,000.00 - $185,000.00 per year

Benefits

• Competitive compensation
• Great benefits
• Workstyle within an environment of shared collaboration, transparency, and inclusivity
• Tools and resources to succeed
• Opportunities to grow and develop

About the Company

• Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
• Across enterprise, cloud and AI, and carrier architectures, Marvell's innovative technology is enabling new possibilities.
• At Marvell, you can affect the trajectory of entire industries, and fuel the transformative potential of tomorrow.
• For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
• Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models.

Equal Opportunity

• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.