Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

About the Role

We are seeking an ASIC Physical Design Engineer to design, test, and deploy advanced hardware within our Ultra Low Latency team. This role involves collaboration across trading, networking, and research infrastructure. It's a unique opportunity for engineers who can lead with physical design expertise while also thinking like chip designers, comfortable owning a full PD flow and reasoning about design decisions across the front-end/back-end boundary. We value engineers excited about improving hardware engineering productivity and reliability through advanced tools like Hardcaml.

Responsibilities

Design, test, and deploy advanced hardware.
Collaborate with teams in trading, networking, and research infrastructure.
Own a physical design flow end-to-end.
Read and write RTL.
Reason about design decisions that cross the front-end/back-end boundary.
Use software engineering techniques to improve the hardware design process.

Requirements

8+ years of hands-on experience building and running modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis).
Broad experience across physical design to own a flow end-to-end and identify risks.
Ability to read and write RTL and understand how front-end design decisions affect physical implementation, and vice versa.
Think about physical design in the context of the overall chip.
Experience programming in a high-level language (Python, C++, Haskell, etc.).
Fluent in English.

Skills

Physical Design
Floorplanning
Place and Route
Timing Closure
Physical Verification
Power Analysis
RTL Design
OCaml (will be taught)
Python
C++
Haskell

Experience Level

8+ years

About the Company

We are big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering.
We created Hardcaml, a hardware development toolchain embedded in OCaml.