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About the Role
We are seeking an experienced ASIC Engineer to design, test, and deploy advanced hardware designs within our Ultra Low Latency team. This role offers collaboration across trading, networking, and research infrastructure, with opportunities to work on both FPGA-based and ASIC-based technologies.
Responsibilities
- Design, test, and deploy advanced hardware designs.
- Collaborate with teams in trading, networking, and research infrastructure.
- Contribute to projects utilizing both FPGA-based and ASIC-based technologies.
- Utilize software engineering techniques to enhance the hardware design process.
Requirements
- 4+ years of practical experience in RTL design and verification.
- Experience with ASIC design using Synopsys or Cadence flows.
- Experience in at least one of the following: Front-end RTL design and synthesis, Back-end physical design, or Verification (including formal).
- Interest in using software engineering techniques to improve the hardware design process.
- Experience programming in high-level languages such as Python, C++, Java, or Haskell.
Skills
- RTL design
- RTL verification
- ASIC design
- Synopsys flows
- Cadence flows
- Front-end RTL design
- Synthesis
- Back-end physical design
- Formal verification
- Python
- C++
- Java
- Haskell
Experience Level
- 4+ years practical experience
About the Company
- We are big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering.
- We created Hardcaml, a hardware development toolchain embedded in OCaml.
- We are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.