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About the Role

We are seeking an ASIC Physical Design Engineer to design, test, and deploy advanced hardware within our Ultra Low Latency team. This role involves collaboration across trading, networking, and research infrastructure. It's a unique opportunity to lead with physical design expertise while thinking like a chip designer, owning the PD flow end-to-end and contributing to RTL design and front-end/back-end boundary decisions. We value engineers who are excited about improving hardware engineering through better tools, specifically our Hardcaml toolchain.

Responsibilities

Design, test, and deploy advanced hardware.
Collaborate with teams in trading, networking, and research infrastructure.
Own a physical design flow end-to-end.
Read and write RTL.
Reason about design decisions that cross the front-end/back-end boundary.
Improve the hardware design process using software engineering techniques.

Requirements

8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis).
Broad experience across physical design to own a flow end-to-end and identify risks.
Ability to read and write RTL and understand how front-end design decisions affect physical implementation, and vice versa.
Think about physical design in the context of the overall chip.
Interest in using software engineering techniques to improve the hardware design process.
Experience programming in a high-level language (Python, C++, Haskell, etc.).

Skills

Physical Design
Floor Planning
Place and Route
Timing Closure
Physical Verification
Power Analysis
RTL Design
OCaml (will be taught)
Python
C++
Haskell

Experience Level

8+ years

About the Company

We are big believers in the ability of tools to improve the productivity, reliability, and day-to-day joy of hardware engineering.
We created Hardcaml, a hardware development toolchain embedded in OCaml.