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About the Role

As a CPU Core Design Verification Engineer, you will verify new and existing microarchitectural features in AMD's next-generation x86 CPU cores. You will independently own a portion of the unit- or core-level verification effort, developing tests, checkers, and coverage, and driving them to a quality result with limited supervision. Collaborate with RTL designers, architects, and fellow verification engineers to ensure microarchitectural intent is correctly implemented and validated.

Responsibilities

Collaborate with RTL designers, architects, and verification engineers to understand microarchitectural features, corner cases, and verification requirements
Own the test plan, stimulus, checking, and functional coverage for an assigned portion of unit- or core-level verification
Design, implement, and maintain C++-based and SystemVerilog-based testbench components, applying modular, reusable verification agent patterns
Write and maintain SystemVerilog assertions and functional coverage models
Debug simulation failures, independently drive root-cause analysis, and work cross-functionally to resolve RTL or testbench issues
Drive functional and code coverage closure for your area, identify verification gaps, and improve stimulus and checking as needed
Apply AI-assisted and agent-based development tools to improve verification productivity

Requirements

Strong interest in computer architecture and processor microarchitecture
Enjoy working at the intersection of hardware and software
Self-motivated problem solver who takes responsibility for the quality and timeliness of your portion of the project
Plan your work over a horizon of weeks to months
Value clean, scalable verification environments
Apply sound testbench and agent principles in your work
Make technical decisions independently within your area
Put checks and balances in place to catch issues early
Communicate clearly
Collaborate effectively across teams and time zones
Good understanding of computer architecture
Experience using C++ and SystemVerilog to develop verification infrastructure for complex hardware designs
Working knowledge of Digital Logic Design and RTL design concepts using Verilog
Familiarity with constrained-random testing and coverage-driven verification
Understanding of assembly-level programming and instruction execution at the ISA level
Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
Scripting knowledge (Python, Perl) is a plus

Skills

C++
Verilog
SystemVerilog
Computer Architecture
Processor Microarchitecture
Hardware
Software
Testbench Development
Agent Principles
Digital Logic Design
RTL Design
Constrained-Random Testing
Coverage-Driven Verification
Assembly-Level Programming
ISA Level Instruction Execution
Formal Tools
Functional Verification Tools
VCS
Cadence
Mentor Graphics
Python
Perl
AI-assisted development tools
Agent-based development tools

Location

Austin, TX

Work Type

Hybrid

Education Level

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits

AMD benefits at a glance

About the Company

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems.
Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.
We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Join us as we shape the future of AI and beyond.
Together, we advance your career.

Equal Opportunity

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.