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About the Role

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are building a center of excellence for Intellectual Property (IP) applied to high-performance computing devices. This role will shape the physical implementation and methodology innovation for high-performance GPU and system-level IP, enabling market-differentiating power, performance, and area (PPA) goals across Samsung’s advanced technology nodes.

Responsibilities

Contribute to key stages of the physical design flow, with a particular focus on top-level floorplanning and power-grid implementation.
Advance implementation strategies, methodology innovation, and scalable execution across parallel development cycles.
Collaborate closely with hardware, advanced design technology, and system-level teams to resolve complex implementation challenges.
Deliver robust, high-quality silicon for advanced-node designs.
Shape full-chip and block-level implementation, including top-level floorplanning, placement, routing, timing closure, and signoff for complex GPU and SoC designs.
Contribute to implementation strategies to achieve market-differentiating PPA targets, including power-grid design and implementation, power optimization, congestion management, STA-driven convergence, and reliability considerations.
Advance methodology and flow innovation, including automation, tool optimization, and scalable design practices, including developing or rewriting physical design flows.
Collaborate cross functionally with architecture, RTL, advanced design technology, software, system-level teams, and external vendors, influencing top-level floorplanning decisions and providing technical guidance to block implementers.
Inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation, and promoting continuous learning.

Requirements

11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
7+ years of hands-on experience with full physical design implementation flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff.
Strong expertise in top-level floorplanning for complex GPU or SoC designs, low-power design, physical verification (DRC/LVS), and advanced-node challenges.
Hands-on power-grid design and implementation experience using PNR tools (FusionCompiler, Innovus or equivalent).
Proficiency in power-grid robustness analysis using (RedHawk or equivalent).
Experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerations.
Strong proficiency with industry-standard EDA tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC).
Strong proficiency with PNR/physical-design tools, commands, and toolflows.
Strong scripting and automation skills in Python, Tcl, Shell, or Perl.
Strong analytical, debugging, and problem-solving skills with a data-driven approach for complex flow and design challenges.
Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers.
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.
Package and power-only layer experience is a plus.
Experience with advanced-node designs (≤5nm) and high-performance GPU or SoC programs.
Experience with DTCO methodologies and implementation scalability challenges.
Low-power partitioning, congestion awareness, layout-integration and feed-through/pin management experience.
Automation/flow-level methodology (beyond ad-hoc scripting).
Experience with floorplanning methodologies and physical-design tradeoffs.
Ability to access information subject to U.S. export control restrictions.
Must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.
Agree not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.

Skills

Physical Design
Methodology Innovation
GPU IP Implementation
Power, Performance, and Area (PPA)
Advanced Technology Nodes
Top-Level Floorplanning
Power-Grid Implementation
Scalable Execution
Full-Chip Implementation
Block-Level Implementation
Placement
Routing
Timing Closure
Signoff
Power Optimization
Congestion Management
STA-Driven Convergence
Reliability Considerations
Automation
Tool Optimization
Design Practices
Cross-Functional Collaboration
Mentoring
Synthesis
Clock Tree Synthesis (CTS)
Low-Power Design
Physical Verification (DRC/LVS)
PNR Tools (FusionCompiler, Innovus or equivalent)
Power-Grid Robustness Analysis (RedHawk or equivalent)
Timing Analysis
Signal Integrity
EDA Tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC)
PNR/Physical-Design Tools
Scripting (Python, Tcl, Shell, Perl)
Analytical Skills
Debugging
Problem-Solving
Data-Driven Approach
Technical Initiative Leadership
Process Innovation
Communication Skills
Package and Power-Only Layer Experience
Advanced-Node Designs (≤5nm)
High-Performance GPU or SoC Programs
DTCO Methodologies
Implementation Scalability
Low-Power Partitioning
Congestion Awareness
Layout Integration
Feed-through/Pin Management
Flow-Level Methodology
Floorplanning Methodologies
Physical-Design Tradeoffs

Location

Austin, TX

Work Type

Full-time
Exempt

Experience Level

Senior Staff
11+ years of experience with a Bachelor’s Degree
9+ years of experience with a Master’s Degree
7+ years of experience with a Ph.D.
7+ years of hands-on experience with full physical design implementation flows

Education Level

Bachelor’s Degree in Computer Science/Engineering
Master’s Degree
Ph.D.

Salary/Compensations

$180,200 - $270,400

Benefits

Medical
Dental
Vision
Life Insurance
401(k)
Onsite Lunch
Employee Purchase Program
Tuition Assistance (after 6 months)
Paid Time Off
Student Loan Program
Wellness Incentives
MBO Bonus Compensation
Long Term Incentive Plan (potential)
Relocation (potential)

About the Company

Samsung is a world leader in advanced semiconductor technology.
Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are building a center of excellence for Intellectual Property (IP) applied to high-performance computing devices (mobile, automotive, and other custom market segments).
The Advanced Design Technology and Design Implementation teams play a critical role in enabling GPU and system-level development within Samsung SARC/ACL and the broader System LSI organization.
Operating at the intersection of design technology and physical implementation, we partner closely with Foundry from early technology exploration through the full development cycle.
Spanning advanced design methodologies, GPU physical design, CAD, and DTCO, we accelerate adoption of leading technology nodes and deliver optimized power, performance, area (PPA), silicon quality, and turnaround time for next-generation IP solutions.
You will join a highly collaborative, fast-paced environment working across parallel development cycles with direct impact on consumer technologies used worldwide.

Equal Opportunity

Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.