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About the Role

As an ASIC Technical Lead, you will drive cutting-edge Design-for-Test (DFT) strategies, bridging the gap between front-end RTL, physical design, and post-silicon validation to ensure elite quality for complex ASICs. Your technical leadership and custom DFT solutions will directly fuel the next generation of best-of-breed routing and switching systems.

Responsibilities

• Implement Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics.
• Develop innovative DFT IP in collaboration with multi-functional teams and coordinate testability features in RTL.
• Work closely with design, design-verification, and PD teams to enable integration and validation of test logic.
• Participate in the creation of innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die.
• Drive re-usable test and debug strategies.
• Craft solutions and debug with minimal mentorship.

Requirements

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
• Prior verification experience including System Verilog Logic Equivalency checking and validating the Test-timing of the design.
• Prior experience with Tcl and Python/Perl.

Skills

• Jtag protocols
• Scan and BIST architectures
• Memory BIST
• Boundary scan
• Post silicon debug
• ATPG
• TestMax
• Tetramax
• Tessent tool sets
• PrimeTime
• System Verilog
• Logic Equivalency checking
• Tcl
• Python
• Perl
• Verilog design
• Custom DFT logic & IP integration
• Functional verification
• DFT CAD development
• Test Architecture
• Methodology
• Infrastructure

Location

• U.S.
• Canada

Work Type

• Full-time

Experience Level

• Bachelors + 8 years
• Masters + 6 years
• PhD + 3 years

Education Level

• Bachelors
• Masters
• PhD

Salary/Compensations

• $186,900.00 - $267,700.00 (U.S. and/or Canada)
• $186,900.00 - $307,800.00 (New York City Metro Area)
• $166,300.00 - $274,100.00 (Non-Metro New York state & Washington state)

Benefits

• Medical insurance
• Dental insurance
• Vision insurance
• 401(k) plan with Cisco matching contribution
• Paid parental leave
• Short-term disability coverage
• Long-term disability coverage
• Basic life insurance
• Restricted stock units
• 10 paid holidays per full calendar year
• 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday
• Paid year-end holiday shutdown
• 4 paid days off for personal wellness
• 16 days of paid vacation time per full calendar year (non-exempt)
• Flexible vacation time off program (exempt)
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• Up to 80 hours of unused sick time carried forward
• Additional paid time away for critical or emergency family issues
• Optional 10 paid days per full calendar year to volunteer
• Annual bonuses (non-sales roles)
• Performance-based incentive pay (sales roles)

About the Company

• Cisco is revolutionizing how data and infrastructure connect and protect organizations in the AI era.
• Cisco has been innovating for 40 years to create solutions that power how humans and technology work together across physical and digital worlds.
• Cisco's solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
• The company fosters experimentation and creation of meaningful solutions.
• Cisco has a worldwide network of doers and experts, offering limitless opportunities to grow and build.
• The company emphasizes teamwork, collaboration, and empathy to achieve large-scale impact.

Equal Opportunity

• Cisco is an equal opportunity employer.