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About the Role

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s “Intelligent Cloud” mission by delivering core infrastructure and foundational technologies for Microsoft's online businesses. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages Microsoft's computer chips, including Azure Cobalt. This role is crucial for defining and delivering operational measures of success for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability for Microsoft's cloud hardware.

Responsibilities

Responsible for SOC low power design methodology and power signoff.
Drive methodology exploration activities to optimize SOC blocks for power, performance, and area (PPA).
Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners.
Responsible for RTL to GDS implementation in Physical Design domain.
Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.
Demonstrate technical expertise across various domains of Physical Design.
Clear communications on project status & planning.
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
7+ years of experience in semiconductor design.
Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
Production silicon tape-outs experience in advanced foundry process nodes.
Experience in low power design methodology for SOC
Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
Familiarity with industry-standard power analysis EDA tools (such as PrimePower)
Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
Own complete PD execution of medium to large-size SOC block. Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required.
Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues
Strong problem-solving and data analysis skills
Ability to communicate effectively with cross-functional teams
Ability to meet Microsoft, customer and/or government security screening requirements.
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Must provide proof of citizenship or US residency for assessment of eligibility to access export-controlled information.
Successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Skills

Power analysis/optimization
SOC low power design methodology
Power signoff
PPA optimization
RTL to GDS implementation
Synthesis
Place-and-route
Timing signoff
Physical verification
EMIR
Formal equivalence
Low-power verification
Physical Design
Problem-solving
Data analysis
Communication
Collaboration
Teamwork

Location

U.S.

Work Type

Full-time

Experience Level

Senior
IC4

Education Level

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Salary/Compensations

USD $119,800 - $234,700 per year (U.S. typical base pay range)
USD $160,200 - $261,000 per year (San Francisco Bay area and New York City metropolitan area)

Benefits

Certain roles may be eligible for benefits and other compensation.

About the Company

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.
SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.
Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt.
Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance.

Equal Opportunity

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.