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About the Role

Join our Digital Design Engineering group to transform imaginative ideas into reality. You will design state-of-the-art ASICs and create extraordinary custom digital macros and libraries using the latest technology nodes. This role offers endless learning opportunities within a fast-paced environment, collaborating with integration, CAD, circuit, and technology engineering teams.

Responsibilities

• Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies.
• Reviewing and analyzing floorplans and complex circuits with circuit designers.
• Running a complete set of layout design verification tools available on megacells completed.
• Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs.
• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layouts.
• Exceeding engineering specifications and expectations.
• Using advanced CAD tools and mask design knowledge for layout corrections and robust physical design representation of circuits.

Requirements

• Bachelors degree in relevant field of study.
• 10 years of relevant experience.
• Experience in custom layout design of deep SubMicron CMOS circuits.
• High level proficiency in layout floorplanning, standard cell planning and hierarchical layout assembly.
• Good understanding of issues with RC delay, electromigration, self heating and cross capacitance.
• Ability to recognize failure prone layout structures and work with designers for the best approach to problems.
• Excellent communication skills and ability to work with multi-functional teams.
• Great skills in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
• Knowledge of MENTOR GRAPHICS or CADENCE layout tools.

Skills

• Custom layout design
• Deep SubMicron CMOS circuits
• Layout floorplanning
• Standard cell planning
• Hierarchical layout assembly
• RC delay
• Electromigration
• Self heating
• Cross capacitance
• CALIBRE DRC
• CALIBRE ERC
• CALIBRE LVS
• MENTOR GRAPHICS layout tools
• CADENCE layout tools
• CSH scripting
• PERL scripting
• SKILL scripting
• Layout automation
• Memory compiler development
• Low noise datapath layout
• Low power datapath layout
• Memory layout structures

Location

• Onsite

Work Type

• Full-time

Experience Level

• 10 years of relevant experience

Education Level

• Bachelors degree

About the Company

• Apple's custom layout team is responsible for designing state-of-the-art ASICs.
• We are an exciting silicon design group responsible for designing state-of-the-art ASICs.
• We have an extraordinary opportunity for Digital Layout Designers.