Design Verification Architect / Director at Cadence Design Systems | California | Rezi

Design Verification Architect / Director at Cadence Design Systems

Design Verification Architect / Director

Cadence Design Systems · California

Yesterday

Design Verification Architect / Director

Cadence Design Systems · California

a day ago
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About the Role

Lead and run the Processor Verification team, responsible for the verification of microprocessor cores and their peripherals. Crafting verification plans and executing them to verify highly complex CPU designs.

Responsibilities

  • Lead and run the Processor Verification team.
  • Responsible for the verification of microprocessor cores and their peripherals.
  • Craft verification plans and execute them to verify highly complex CPU designs.
  • Implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
  • Responsible for coverage collection and closure.
  • Work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope.
  • Track and report the work of 7-10 engineers.

Requirements

  • 17+ years of design verification experience.
  • Proven experience in leading/managing a team.
  • Strong managerial, leadership, and interpersonal skills.
  • Excellent knowledge of computer architecture and design verification fundamentals.
  • Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches.
  • Exposure to scripting languages like Perl, Unix shell or similar languages.
  • Experience with assembly language programming required.
  • Experience with Formal Verification will be a plus.
  • Experience with the development of fully automated flows.
  • Experience with Gate Level Simulations.
  • Excellent written and oral communication skills necessary.
  • Knowledge of processor verification required.

Skills

  • System Verilog
  • UVM
  • Perl
  • Unix shell
  • Assembly language programming
  • Formal Verification
  • Gate Level Simulations

Location

  • California

Work Type

  • Full-time

Experience Level

  • 17+ years of design verification experience
  • Proven experience at leading/managing team

Education Level

  • BS (or higher) in EE/Computer Engineering

Salary/Compensations

  • $178,500 to $331,500

Benefits

  • Incentive compensation: bonus, equity
  • Paid vacation and paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Variety of medical, dental and vision plan options

About the Company

  • At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • We’re doing work that matters. Help us solve what others can’t.