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About the Role

Meta is seeking an ASIC Design Verification Engineer to join the Infrastructure Silicon organization. This role focuses on building IP and System on Chip (SoC) solutions for data center applications, requiring ownership of verification closure for design modules or sub-systems. You will utilize simulation, formal verification, and emulation methodologies, collaborating with various teams to ensure first-pass silicon success.

Responsibilities

Define and implement block, IP, and SoC-level verification plans to enable comprehensive functional coverage across design hierarchies.
Develop and maintain UVM-based testbenches and functional test sequences aligned to the verification test plan.
Drive verification closure using defined metrics including functional coverage, code coverage, and assertion coverage.
Debug and root-cause functional failures in RTL designs, partnering closely with the ASIC design team to resolve issues.
Apply formal verification and emulation techniques to complement simulation-based approaches and improve verification efficiency.
Collaborate with design, architecture, and post-silicon validation teams to align on verification goals and ensure design quality.
Develop reusable verification infrastructure components including scoreboards, monitors, and coverage models.
Contribute to scripting and automation flows using Python, TCL, or Shell to improve verification productivity and regression management.
Participate in design reviews and verification planning discussions to identify potential design risks early in the development cycle.

Requirements

Currently have, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
2+ years of hands-on experience in SystemVerilog and UVM-based verification methodology or C/C++ based hardware verification.
2+ years of experience in block, IP, sub-system, or SoC-level verification using SystemVerilog UVM or OVM methodologies.
Experience with EDA simulation tools and scripting languages such as Python, TCL, Perl, or Shell for building verification environments and flows.
Experience debugging RTL functional failures and performing root-cause analysis in a simulation or emulation environment.

Skills

SystemVerilog
UVM
OVM
C/C++
Python
TCL
Perl
Shell
Formal verification
Emulation

Location

Remote

Work Type

Full-time

Experience Level

2+ years

Education Level

Bachelor's degree

Salary/Compensations

$114,000/year to $172,000/year

Benefits

bonus
equity

About the Company

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization.
We are looking for individuals with experience in Design Verification to build IP and System on Chip (SoC) solutions for data center applications.
In this role, you will work alongside experienced engineers focused on developing advanced ASIC solutions that power Meta's data center infrastructure.