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About the Role

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon powering Meta's data center infrastructure. You will architect and drive end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and storage workloads.

Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
• Develop functional tests based on the verification test plan
• Drive design verification to closure based on defined verification metrics on the test plan, functional, and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the design team
• Collaborate with cross-functional teams like Design, Model, Emulation, and silicon validation teams towards ensuring the highest design quality
• Develop and drive continuous design verification improvements using the latest verification methodologies, tools, and technologies from the industry

Requirements

• Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
• 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
• 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in one or more of the following areas, along with functional verification, SV assertions, formal, and emulation
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience in architecting and implementing design verification infrastructure and executing the full verification cycle
• Familiarity with power management verification concepts
• Experience verifying compute, memory, or interconnect subsystems within AI/ML accelerator or data center networking SoCs
• Experience with ARM, RISC-V, or GPU-based subsystem verification at the IP or full-chip level
• Familiarity with host and system-level software stacks as they relate to hardware functional verification and stimulus generation
• Experience with chiplet-based architectures and package-level integration verification methodologies

Skills

• SystemVerilog/UVM
• C/C++
• SystemVerilog UVM/OVM
• SV assertions
• Formal verification
• Emulation
• EDA tools
• Python
• TCL
• Perl
• Shell scripting
• Power management verification
• ARM
• RISC-V
• GPU-based subsystem verification
• Host and system-level software stacks
• Chiplet-based architectures
• Package-level integration verification

Location

• Meta's data center infrastructure

Work Type

• Full-time

Experience Level

• Staff
• 8+ years

Education Level

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field

Salary/Compensations

• $178,000/year to $250,000/year

Benefits

• bonus
• equity

About the Company

• Meta's Infrastructure Silicon team designs and builds custom silicon powering Meta's data center infrastructure.