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About the Role

The Interface IP Team within Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer-focused solutions, insight, and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

Responsibilities

Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows.
Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across MMMC corners.
Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements.
Run, review, and debug physical design flows and timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations.
Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA.
Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT)
8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs
Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints
Experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)
Proficiency in recent synthesis tool capabilities and methods for QoR improvement
Proficiency in static timing analysis
Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification
Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines
Proficiency in translating physical design results into feedback for flow or RTL improvement
Proficiency in Tcl, Python
Knowledge of full RTL2GDS flow
Ability to meet Microsoft, customer and/or government security screening requirements.
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Must provide proof of citizenship or US residency for export control regulations assessment.
Must provide a valid passport for citizenship verification.

Skills

Digital and mixed-signal block design
Static timing analysis
RTL design
Design checks (CDC/RDC/VCLP/LINT)
Synthesis
Timing constraints
Power Performance Area (PPA) trade-offs
RTL to Physical Design collateral development
Industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)
Synthesis tool capabilities for QoR improvement
Gate-level power analysis/optimization
UPF
Power-intent verification
Project-level tool setup and configuration
Tcl
Python
RTL2GDS flow

Location

U.S.

Work Type

Full-time

Experience Level

Senior
1+ year(s) technical engineering experience
4+ years technical engineering experience
5+ years technical engineering experience
8+ years of experience

Education Level

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Salary/Compensations

USD $119,800 - $234,700 per year (U.S. typical base pay range)
USD $160,200 - $261,000 per year (San Francisco Bay area and New York City metropolitan area)

Benefits

Eligible for benefits and other compensation

About the Company

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.
SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.
Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide.

Equal Opportunity

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.