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About the Role

Meta's Silicon Engineering team develops custom silicon for AI and data center workloads. As an ASIC Engineer, you will manage the physical implementation of custom chips from RTL to tapeout, covering synthesis, place-and-route, timing closure, and signoff. You will collaborate with cross-functional teams to deliver high-performance, power-efficient silicon for Meta's next-generation infrastructure.

Responsibilities

• Develop timing constraints for RTL-Synthesis and PrimeTime-STA for blocks and the top-level SOC.
• Analyze inter-block timing and establish IO budgets for partition blocks.
• Develop SOC timing full chip flat & hierarchical constraints for functional & DFT modes.
• Perform STA for full chip and physical partition blocks using PrimeTime.
• Run logic/physical synthesis using advanced optimization techniques to generate optimized Gate Level Netlists for timing, area, and power.
• Develop automation scripts and methodologies for front-end tools, including synthesis and STA.
• Collaborate with Design, DV, and Emulation Engineers to support handoff tasks.
• Interact with Physical Design Engineers to provide timing/congestion feedback.

Requirements

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 6+ years of experience with Timing Analysis.
• Experience developing full chip flat & hierarchical timing constraints.
• Experience with AOCV/POCV timing analysis and SI noise analysis.
• Experience running Static Timing Analysis for full chip using DMSA.
• Knowledge of front-end and back-end ASIC flows.
• Experience communicating across functional internal teams and vendors.

Skills

• Timing Analysis
• SOC Design Integration
• Front End Implementation
• Back End PD tools (Fusion Compiler, Innovus)
• Front End Synthesis tools (Design Compiler, Genus)
• AOCV/POCV timing analysis
• SI noise analysis
• Static Timing Analysis (DMSA)
• ASIC flows
• RTL-Synthesis
• PrimeTime-STA
• PrimeTime
• Logic/Physical Synthesis
• Automation scripts

Location

• Silicon Valley

Work Type

• Full-time

Experience Level

• 6+ years of experience with Timing Analysis

Education Level

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Salary/Compensations

• $146,000/year to $209,000/year

Benefits

• bonus
• equity
• benefits

About the Company

• Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads at scale.