ASIC Implementation Engineer - Static Verification at Meta | Austin, TX, US | Rezi

ASIC Implementation Engineer - Static Verification at Meta

ASIC Implementation Engineer - Static Verification

Meta · Austin, TX, US

1 months ago

ASIC Implementation Engineer - Static Verification

Meta · Austin, TX, US

a month ago
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About the Role

Meta is hiring ASIC Frontend Implementation Engineers to design efficient System on Chip (SoC) and IP for data center applications. This role involves front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis.

Responsibilities

  • Perform Flat and Hierarchical Clock Domain Crossing and work with designers to analyze and sign off complex clock domain crossings.
  • Perform Flat and Hierarchical Reset Domain crossing Checks, develop reset groups, and corresponding reset sequences.
  • Perform RTL Lint and collaborate with designers to create waivers.
  • Perform RTL DFT Analysis and enhance DFT coverage for Stuck-at faults.
  • Run Logic/Physical Synthesis using advanced optimization techniques to generate optimized Gate Level Netlist for Timing, Area, and Power.
  • Develop automation scripts and methodologies for FE-tools (Lint, CDC, RDC).
  • Collaborate with Design, DV, and Emulation Engineers on handoff tasks.
  • Interact with Physical Design Engineers to provide timing/congestion feedback.

Requirements

  • Currently have, or be in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
  • 2+ years of experience in static verification tools.
  • Experience with Lint, Clock Domain & Reset Domain crossing.
  • Experience with SOC CDC signoff.
  • Knowledge of SOC Integration (Clocking, Reset, PLL, etc).
  • Knowledge of front-end ASIC flows.
  • Experience with RTL design using SystemVerilog or other HDL.
  • Experience communicating across functional internal teams and vendors.

Skills

  • Lint
  • Clock Domain Crossing (CDC)
  • Reset Domain Crossing (RDC)
  • RTL Lint
  • DFT Analysis
  • Logic Synthesis
  • Physical Synthesis
  • Gate Level Netlist generation
  • Automation scripting
  • SystemVerilog
  • Perl
  • Python
  • TCL
  • Make
  • Design Compiler
  • Spyglass
  • PrimeTime
  • Formality

Location

  • Remote

Work Type

  • Full-time

Experience Level

  • 2+ years

Education Level

  • Bachelor's degree

Salary/Compensations

  • $114,000/year to $172,000/year

Benefits

  • Bonus
  • Equity
  • Benefits

About the Company

  • Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization.