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About the Role

We seek a motivated Senior Digital ASIC Design Engineer to join our team as a senior digital designer for developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.

Responsibilities

Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs
Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders
Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces
Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration
Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments
Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration
Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout
Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems
Lead technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies

Requirements

Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study
Minimum seven (7) years of progressively responsible related work experience in digital ASIC design
Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs
Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation
Experience with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems
Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges
Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams

Skills

SystemVerilog
Verilog
ASIC design
RTL design
Microarchitecture
Digital ASIC design
Low-power design
Radiation-aware design
Timing-critical systems
Data-intensive systems
Scientific applications
Mixed-signal ASICs
Detector readout
Trigger and timing distribution
Data concentration
Control systems
Calibration systems
High-speed data transmission
Analog designers
Mixed-signal designers
Verification engineers
Physical design engineers
Firmware developers
Detector scientists
Radiation detectors
Readout electronics
Data acquisition systems
Scientific instrumentation
Electron-Ion Collider (EIC)
ePIC detector systems
High-energy physics
Nuclear physics
Photon sciences
Quantum information science
Synthesis
Static timing analysis
Clock-domain crossing analysis
Reset-domain crossing analysis
Power estimation
Linting
Design-for-test insertion
Timing-driven physical implementation
Cadence
Synopsys
Siemens
CAD/EDA environments
Floorplanning
Partitioning
Timing closure
Power integrity
Signal integrity
Verification plans
Self-checking test benches
Functional coverage
Simulation debugging
FPGA prototyping
Laboratory evaluation
Test-board development
ASIC bring-up
ASIC characterization
Technical documentation
Design reviews
Interface control documents
Project proposals
Microelectronics
Master's degree
Ph.D.
Readout integrated circuits
Detector timing
Sparsified data readout
High-speed data transmission
Calibration functions
Slow-control functions
Particle physics
Cryogenic instrumentation
Space environments
Radiation environments
Digital implementation tools
Automated place and route
AXI
AHB
APB
Wishbone
I2C
SPI
JTAG
Custom detector-readout protocols
Scripting
Automation
Tcl
Python
Perl
Make
Shell scripting
EDA environment
Radiation-tolerant design techniques
Single-event-effect mitigation
Triple modular redundancy
Error detection/correction
Low-power operation
Cryogenic operation
Firmware
Board-level test systems
Laboratory characterization

Location

Upton, NY

Work Type

Onsite
Fully onsite

Experience Level

Senior
Minimum seven (7) years of progressively responsible related work experience

Education Level

Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study
Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study

Salary/Compensations

$115000 - $145000 / year

Benefits

Comprehensive employee benefits program

About the Company

Brookhaven National Laboratory (www.bnl.gov) delivers discovery science and transformative technology to power and secure the nation’s future.
Brookhaven Lab is a multidisciplinary laboratory with seven Nobel Prize-winning discoveries, 37 R&D 100 Awards, and more than 70 years of pioneering research.
The Lab is primarily supported by the U.S. Department of Energy’s (DOE) Office of Science.
Brookhaven Science Associates (BSA) operates and manages the Laboratory for DOE.
BSA is a partnership between Battelle and The Research Foundation for the State University of New York on behalf of Stony Brook University.
BSA salutes our veterans and active military members with careers that leverage the skills and unique experience they gained while serving our country, learn more at BNL | Opportunities for Veterans at Brookhaven National Laboratory.

Equal Opportunity

Guided by our core values of integrity, responsibility, innovation, respect, and teamwork, Brookhaven Science Associates is an Equal Employment Opportunity Employer-Vets/Disabled.
We are committed to fostering a respectful and collaborative environment that fuels scientific discovery.
We consider all qualified applicants without regard to any characteristic protected by law.
All qualified individuals are encouraged to apply.
We ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment.
Please contact us to request accommodation.
*VEVRAA Federal Contractor
BSA employees are subject to restrictions related to participation in Foreign Government Talent Recruitment Programs, as defined and detailed in United States Department of Energy Order 486.1A.
You will be asked to disclose any such participation at the time of hire for review by Brookhaven.
The full text of the Order may be found at: https://www.directives.doe.gov/directives-documents/400-series/0486.1-BOrder-a/@@images/file