Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

About the Role

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is seeking a Principal Engineer – Analog and Mixed-Signal Physical Design to drive physical implementation, timing closure, physical design verification, and custom IP integration for analog and mixed-signal designs. This is a hands-on role requiring deep Fusion Compiler-based physical implementation expertise and strong timing closure and physical verification experience.

Responsibilities

Drive hands-on physical design implementation for analog and mixed-signal IP blocks, including floorplanning, placement, routing, optimization, ECO implementation, and closure debug.
Execute and guide Fusion Compiler-based APR flows, with direct ownership of implementation quality, timing convergence, physical design verification readiness, and signoff closure.
Serve as the technical bridge between analog design, custom layout, physical design, timing, physical verification, CAD/methodology, and silicon integration teams.
Perform timing analysis and closure activities across analog and mixed-signal-adjacent IP, including constraint review, timing debug, implementation tradeoffs, and signoff readiness.
Partner with custom layout engineers to ensure layout feasibility, integration quality, physical verification closure, and timing/implementation convergence.
Lead internal and external/V-team execution through hands-on technical direction, deliverable review, quality expectations, and schedule alignment.
Debug and resolve complex implementation issues related to physical design, timing closure, extraction, physical verification, layout integration, reliability, and release readiness.
Coordinate implementation activities across architecture, circuit design, layout, CAD/methodology, verification, product engineering, and silicon integration stakeholders.
Contribute to design reviews, implementation quality improvements, signoff planning, and broader execution strategy for analog, mixed-signal, and custom IP physical design deliverables.
Mentor engineers and provide Principal-level technical leadership while remaining directly engaged as a doer in critical implementation and closure work.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including Microsoft Cloud Background Check.
Must provide proof of citizenship or US residency for export control regulations assessment.
Successful candidate's citizenship will be verified with a valid passport; lawful permanent residents, refugees, and asylees may verify status using other documents.

Skills

Fusion Compiler-based physical implementation
Timing closure
Physical design verification
Custom IP integration
Analog and mixed-signal IP physical implementation
PrimeTime timing analysis
Constraint debug
Timing ECO strategy
Custom analog layout
Virtuoso-based layout methodologies
Physical verification
Extraction
Layout integration
Advanced-node implementation challenges
Debugging
Analytical skills
Problem-solving skills
Communication skills
Cross-functional collaboration skills
Technical leadership
Fusion Compiler-based APR
Floorplanning
Placement
Clock tree synthesis
Routing
Optimization
ECO implementation
Closure debug
Physical design verification
Implementation signoff
Silicon quality methodologies
Hands-on physical implementation
Timing closure for complex silicon IP
Leading or coordinating distributed engineering teams

Location

U.S.

Work Type

Full-time

Experience Level

Principal
IC5

Education Level

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field

Salary/Compensations

USD $142,800 - $274,800 per year (U.S. typical base pay range)
USD $188,000 - $304,200 per year (San Francisco Bay area and New York City metropolitan area)

Benefits

Certain roles may be eligible for benefits and other compensation.

About the Company

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and is responsible for powering Microsoft’s Intelligent Cloud mission.
SCHIE delivers the core infrastructure and foundational technologies for Microsoft’s online businesses, including Azure, Microsoft 365, Teams, OneDrive, Xbox, and other global services.

Equal Opportunity

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.