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About the Role

Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block, cluster, or full chip level, focusing on netlist aspects like equivalence checking, asynchronous checking, MTBF analysis, logic synthesis, and netlist quality. Assist in all physical design areas, including timing convergence, constraint management, and ECO implementation.

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
• Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

Requirements

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
• Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
• Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
• Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
• Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
• Expertise and in-depth knowledge of industry standard EDA tools in related fields.
• Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

Skills

• Logic equivalence checking
• Formal verification (FV)
• Hardware architecture
• RTL design
• Logic design
• Timing closure
• Clock-domain-crossing checking
• MTBF analysis
• Logic synthesis
• Static Timing Analysis (STA)
• Timing constraints generation
• Timing constraints management
• EDA tools
• Perl
• TCL
• Make
• Python
• Logic synthesis
• Equivalence checking/FV
• Debugging
• Problem-solving
• DFT timing closure
• AI utilization

Location

• Hybrid

Work Type

• Hybrid

Experience Level

• Senior
• 5+ years experience (BS)
• 3+ years experience (MS)

Education Level

• BS in Electrical or Computer Engineering
• MS in Electrical or Computer Engineering

Salary/Compensations

• 136,000 USD - 218,500 USD (Level 3)
• 168,000 USD - 264,500 USD (Level 4)

Benefits

• Equity
• Benefits

About the Company

• NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.
• NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
• NVIDIA uses AI tools in its recruiting processes.

Equal Opportunity

• NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.