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About the Role

We are seeking a highly skilled and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team. The ideal candidate will have a deep understanding of the physical verification process in the context of semiconductor design and manufacturing. This role involves working closely with design and layout teams to ensure the integrity and performance of Marvell's advanced semiconductor products.

Responsibilities

Develop run sets for nanotechnology and support Calibre, ICV and provide user support for DRC and LVS debugging to streamline physical verification flow.
Automate and support physical verification flow for internal design tools group.
Support tape-out and design-related foundry interface activities, physical verification CAD flow, and CAD flows for SOC integration.
Develop and maintain validation procedures for physical verification flow and prepare user guides and documents.
Review results and create validation test cases using full custom layout tools.
Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design, verification, and physical implementation.
Integrate various EDA tools into an efficient and cohesive design flow, ensuring seamless interoperability and maximizing design productivity.
Define and optimize design methodologies, flows, and best practices for efficient and reliable chip design, from physical verification to SoC tapeout.
Automate design tasks, including physical verification flow, design rule decks, and automate layout migration, to improve design efficiency and reduce time-to-market.
Evaluate and select third-party EDA tools, libraries, and IPs to meet project requirements, considering performance, scalability, and cost-effectiveness.
Collaborate with cross-functional teams, including foundry engineers, design engineers, layout designers, and software developers, to provide technical guidance, support, and training on CAD and EDA tools and methodologies.
Monitor and optimize tool performance, addressing any issues or bottlenecks, and ensuring tool reliability, stability, and usability across design projects.
Stay up-to-date with the latest advancements in CAD and EDA tools, methodologies, and industry trends, and provide recommendations on incorporating new technologies to enhance design capabilities.
Create and maintain comprehensive documentation, user guides, and training materials for CAD and EDA tools and methodologies, enabling efficient knowledge transfer and onboarding of new team members.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or equivalent professional experience in lieu of a formal degree.
Experience in CAD and EDA tool development and support, preferably within the semiconductor industry.
In-depth knowledge and hands-on experience with industry-standard EDA tools and methodologies for digital and analog IC design, verification, and physical implementation.
Proficiency with tools such as Cadence, Synopsys, Mentor Graphics, and scripting languages like Tcl, Perl, Python.
Synopsys ICV is required, and Mentor Calibre svrf / tvf is preferred.
Strong understanding of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation (place and route, timing analysis, physical verification).
Demonstrated ability to analyze complex design and tool-related issues, propose innovative solutions, and drive them to completion.
Excellent interpersonal and communication skills, with a collaborative mindset and the ability to work effectively with cross-functional teams.
Proven experience in leading projects or initiatives, providing technical guidance, and mentoring junior engineers preferred.
Strong motivation for staying abreast of the latest advancements in CAD and EDA tools and methodologies, and a passion for innovation and continuous improvement.
Candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
Applicants must be eligible to access export-controlled information as defined under applicable law.

Skills

Physical Verification
DRC
LVS
Calibre
ICV
Tcl
Perl
Python
Cadence
Synopsys
Mentor Graphics
Full Custom Layout Tools
SOC Integration
RTL
Synthesis
Simulation
Place and Route
Timing Analysis

Location

Remote

Work Type

Full-time

Experience Level

Senior Staff Level

Education Level

Bachelor's degree in Computer Science, Electrical Engineering or related fields
Master's degree in Computer Science, Electrical Engineering or related fields
PhD in Computer Science, Electrical Engineering or related fields

Salary/Compensations

129,100 - 191,030 USD per annum

Benefits

Employee stock purchase plan with a 2-year look back
Family support programs
Robust mental health resources
Recognition and service awards

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
Across enterprise, cloud and AI, and carrier architectures, Marvell's innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.