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About the Role

As a Staff Design for Test STA Engineer, you will be a key technical leader ensuring the testability, quality, and performance of next-generation AI processors. This role requires expertise in Design for Test (DFT) architecture and implementation, along with Static Timing Analysis (STA) for complex SoCs. You will define and implement DFT methodology, own top-level timing constraints and sign-off for DFT modes, and collaborate with RTL, Physical Design, and Product Engineering teams for silicon success.

Responsibilities

Coordinate DFT requirements across SOC, IP and product teams.
Work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes.
Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions.
Work closely with the Physical Design team to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
Identify and implement improvements to existing DFT and STA flows.
Participate in ATE targeted test patterns, validation and silicon-debug.
Work closely with test and product engineering teams on silicon characterization and validation.

Requirements

Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints.
Proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

Skills

Design for Test (DFT)
Static Timing Analysis (STA)
Scan Compression
Memory BIST
JTAG/IJTAG
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Synopsys PrimeTime
Cadence Tempus
Verilog
SystemVerilog

Location

Santa Clara, CA
Austin, TX

Work Type

Hybrid

Experience Level

Staff
Various experience levels

Salary/Compensations

$100k - $500k

Benefits

Highly competitive compensation package and benefits

About the Company

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.
With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.
We value collaboration, curiosity, and a commitment to solving hard problems.
We are growing our team and looking for contributors of all seniorities.

Equal Opportunity

We are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.
Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).
These requirements apply to persons located in the U.S. and all countries outside the U.S.
As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.