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About the Role

We are seeking a highly experienced technical leader to lead the PDK Architecture team responsible for driving the technical execution of Intel's Process Design Kit (PDK) across leading-edge technology nodes. The position leads a team that serves as the technical leaders for overall PDK execution and the primary bridge between Technology Development, PDK Development, and EDA partners to ensure technology requirements are translated into scalable, high-quality, and customer-ready PDK solutions. The role combines deep technical expertise, cross-functional leadership, customer-focus, and program execution to enable predictable and high-quality PDK deliveries for internal and external customers.

Responsibilities

Lead the definition and specification of PDK scope and content.
Act as primary interface to Technology Definition to align and lock down inputs for PDK.
Drive technology closure and readiness assessments across Logic, SRAM, AMS, APR, Reliability, and Packaging domains.
Drive technical architecture and implementation decisions for the PDK.
Define standards and repeatable processes to streamline and accelerate PDK development.
Develop technology capability roadmaps and ensure PDK commitments align with technology performance objectives and customer requirements.
Lead executive-level reviews to identify and resolve technology readiness gaps before they impact PDK schedules.
Partner with Technology Development organizations to evaluate new process features, design enablement requirements, and ecosystem impact before PDK execution begins.
Define and execute the architecture roadmap for 3DIC and advanced packaging PDK solutions.
Drive development and release of 3DK collateral supporting heterogeneous integration technologies.
Ensure PDK architectures support future chiplet, system-in-package, and heterogeneous integration offerings.
Own PDK specification methodology, quality standards, and governance processes.
Establish machine-readable and AI-enabled specification frameworks that improve automation and traceability.
Ensure specifications accurately translate technology requirements into executable PDK deliverables.
Drive specification signoff processes and cross-functional alignment with Technology Development and Design Enablement teams.
Drive quality, completeness, and traceability of PDK requirements.
Lead specification sign-off processes across Technology Development, PDK Development, and Design Enablement organizations.
Lead globally distributed teams and influence organizations across PDK Development, QA, Infrastructure and Technology Development.
Partner with Program management for PDK execution.

Requirements

MS or PhD in Electrical Engineering, Computer Engineering, Physics, Materials Science, or related discipline.
10+ years in semiconductor technology development, design enablement, EDA, PDK development, CAD, DTCO, or related fields.
Strong communication and executive presentation skills.
Experience with foundry PDK development and release processes.
Understanding of design rules, extraction, modeling, physical verification, custom design flows, APR flows, and validation methodologies.
Experience working with EDA partners such as Synopsys, Cadence, and Siemens.
Knowledge of specification systems, automation frameworks, AI-assisted workflows, and software development methodologies.
Proven experience driving organizational transformation, standardization, and quality improvements.
Should accept this position, you must consent to and pass an extended Background Investigation.

Skills

PDK Architecture
Technical Execution
Technology Development
PDK Development
EDA Partners
Scalable Solutions
High-Quality Solutions
Customer-Ready Solutions
Deep Technical Expertise
Cross-Functional Leadership
Customer Focus
Program Execution
Predictable Deliveries
PDK Targeting
PDK Definition
Technology Definition
Modeling Inputs
Design Rules
Technology Closure
Readiness Assessments
Logic
SRAM
AMS
APR
Reliability
Packaging Domains
Technical Architecture
Implementation Decisions
Standards Definition
Repeatable Processes
Streamlining
Accelerating PDK Development
Technology Capability Roadmaps
Technology Performance Objectives
Customer Requirements
Executive-Level Reviews
Technology Readiness Gaps
PDK Schedules
New Process Features
Design Enablement Requirements
Ecosystem Impact
3DIC Enablement
Advanced Packaging
3DK Collateral
Heterogeneous Integration Technologies
Chiplet
System-in-Package
PDK Specifications
PDK Governance
Specification Methodology
Quality Standards
Governance Processes
Machine-Readable Frameworks
AI-Enabled Frameworks
Automation
Traceability
Executable PDK Deliverables
Specification Signoff
Cross-Functional Alignment
Design Enablement Teams
PDK Requirements
Globally Distributed Teams
PDK Development
QA
Infrastructure
Program Management
Foundry PDK Development
Foundry PDK Release Processes
Extraction
Physical Verification
Custom Design Flows
APR Flows
Validation Methodologies
Synopsys
Cadence
Siemens
Specification Systems
Software Development Methodologies
Organizational Transformation
Quality Improvements
Communication Skills
Executive Presentation Skills

Location

US, California, Santa Clara
US, Arizona, Phoenix
US, Oregon, Hillsboro
US, Texas, Austin

Work Type

On-site
Experienced Hire
Shift 1

Experience Level

10+ years

Education Level

MS or PhD

Salary/Compensations

$233,990.00-330,340.00 USD

Benefits

Competitive pay
Stock bonuses
Benefit programs which include health, retirement, and vacation.

About the Company

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.