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About the Role

As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency of Intel's products, ensuring seamless integration of Design for Test (DFT) capabilities in cutting-edge designs. This role offers the opportunity to collaborate with architecture, design, verification, and manufacturing teams, contributing to the creation of industry-leading SoC and IP solutions. Your work will drive innovation, enhance test coverage, and optimize the power, performance, and area of complex designs, enabling Intel's leadership in silicon design and manufacturing.

Responsibilities

Develop logic design and RTL coding to support DFT features such as SCAN, MBIST, and BSCAN.
Provide timing closure support and test content generation for manufacturing.
Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT.
Optimize designs to meet power, performance, area, timing, and test coverage goals while adhering to design integrity standards.
Write, integrate, and verify RTL and structural code for DFT functionality.
Drive verification efforts to ensure architecture and microarchitecture specifications are achieved.
Support IP and SoC integration to ensure high-quality implementation of DFT blocks.
Develop high-volume manufacturing (HVM) content for rapid bring-up and production on automatic test equipment (ATE).
Collaborate with post-silicon and manufacturing teams to verify features on silicon and document learnings for continuous improvement.
Drive high test coverage through structural and IP-specific tests to achieve product quality and defect-per-million (DPM) objectives.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in DFT, SoC design, or related semiconductor design areas
Tessent Shell flows and SSN methodology
Hands-on experience with ATPG, scan insertion, and/or MBIST/repair
RTL design experience using hardware description languages such as Verilog, VHDL, or SystemVerilog
Tessent Fast IO, ISTK, and related methodologies
Exposure to or interest in large ASIC applications in design or test
Familiarity with advanced DFT techniques for low-power and high-performance SoC designs
Understanding of industry standards such as IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), IEEE 1500 (Core Test), and IEEE 1838
Experience with industry-standard DFT tools such as Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, or Cadence Modus
Proficiency in scripting languages such as TCL, Perl, or Python for design automation
Knowledge of timing constraints, UPF, and low-power design and test methodologies
Experience working across cross-functional teams or contributing to complex SoC projects

Skills

DFT
SoC design
RTL coding
SCAN
MBIST
BSCAN
Timing closure
Test content generation
Architecture definition
Microarchitecture definition
Power optimization
Performance optimization
Area optimization
Test coverage
Design integrity
RTL design
Hardware description languages
Verilog
VHDL
SystemVerilog
Verification
IP integration
SoC integration
High-volume manufacturing (HVM) content
Automatic test equipment (ATE)
Post-silicon verification
Manufacturing collaboration
Defect-per-million (DPM) objectives
Tessent Shell flows
SSN methodology
ATPG
Scan insertion
MBIST/repair
Tessent Fast IO
ISTK
Low-power DFT
High-performance SoC design
IEEE 1687 (IJTAG)
IEEE 1149.1 (JTAG)
IEEE 1500 (Core Test)
IEEE 1838
Siemens EDA (Mentor) Tessent
Synopsys DFT Compiler
Cadence Modus
TCL scripting
Perl scripting
Python scripting
Design automation
Timing constraints
UPF
Low-power design
Low-power test methodologies
Cross-functional team collaboration
Complex SoC projects

Location

US, Texas, Austin

Work Type

On-site
Experienced Hire

Experience Level

5+ years

Education Level

Bachelor's degree

Salary/Compensations

$141,910.00-200,340.00 USD

Benefits

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits

About the Company

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.