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About the Role
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness. In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
Responsibilities
- Developing layout design methodology for testchip development in next generation process nodes
- Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.
- Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
- Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
- Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
- Working with tool/flow owners and vendors for ongoing tool/methodology improvement
Requirements
- Master's degree in electrical engineering or related field with minimum of 5 years of experience
- Experience with physical/layout design in advance technology nodes
- Experience in Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
- Experience with Design rules and layout constraints in advanced semiconductor processes
- Experience with floorplanning, hierarchical design integration, and layout verification/debug
- Experience in Definition of Testchip/Product design from Concept to Execution Commit
- Experience in working with Foundry teams on negotiating features to exercise in design
- Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
- Previous related work experience in a semiconductor foundry preferred
Skills
- Layout design
- Physical design
- SoC integration
- Cadence Virtuoso Suite
- Synopsys Custom Compiler
- Floorplanning
- Hierarchical design integration
- Layout verification
- Debug
- Project Management
Location
- US, Oregon, Hillsboro
- US, California, Santa Clara
- US, Texas, Austin
Work Type
- Hybrid
- Experienced Hire
- Shift 1 (United States of America)
Experience Level
- Minimum of 5 years of experience
Education Level
- Master's degree in electrical engineering or related field
Salary/Compensations
- $141,910.00-200,340.00 USD
Benefits
- Competitive pay
- Stock bonuses
- Health benefits
- Retirement benefits
- Vacation benefits
About the Company
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life
- Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
Equal Opportunity
- All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.