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About the Role

The Principal Design Engineer in Micron’s NVEG organization contributes to the development of new memory products by assisting with the overall design, layout, and optimization of datapath circuits for NAND flash memory. This position will drive task forces and make strategic decisions on major datapath architectural changes influenced by new design specs such as higher speed/lower power. They will assess pros and cons of new architecture and drive all activities pertaining its implementation. The role will be expected to lead technical datapath design projects, directing the design planning, layout, and validation activities according to project timelines.

Responsibilities

Design and optimize TSV interface circuits connecting memory die to logic die including Rx/Tx circuit for internal TSV channels, impedance matching and timing margin analysis.
Develop and characterize TSV electrical models and define circuit design constraints for datapath interface.
Define and implement signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis.
Define and implement power integrity requirements using TSV for highly parallel IO and array operations.
Design and verify TSV-specific DFT circuits including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic.
Interface with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath.
Develop and execute functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression.
Design and optimize the wide internal parallel data bus spanning multiple arrays, channels and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus.
Architect the data path from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface, managing parallelism across bank groups and banks.
Develop clocking and synchronization strategies for the highly parallel internal bus including wave pipeline design, clock distribution, and skew management.
Implement and optimize column redundancy and lane repair schemes compatible with HBM like highly parallel bus architecture.
Define timing budgets and perform timing analysis across the full internal datapath under PVT variations.
Support post-silicon validation, debug and correlation activities; identify schematic edits and drive necessary tape-out revisions.
Collaborate with packaging and assembly teams to ensure TSV reliability constraints are met within the datapath floorplan.
Communicate with project integration and other functional teams in design on specifications of major block interfaces.
Communicate with PE to drive silicon experiments and propose fixes and improvements for yield improvement and silicon debugging.
Communicate with Apps regarding introduction of new specs and limitations based on design requirements and limitations.
Document and review final results with experts and stakeholders.

Requirements

BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND or other high-density memory technologies.
Experience with TSV interface circuit design or high-speed memory interface design(NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity.
Advanced knowledge and understanding of highly parallel bus performance, power and area optimization including clock distribution and skew management across wide data paths, and EpB optimization in the context of 3D-stacked memory architectures.
Experience managing complex circuit design projects spanning multiple functional blocks and cross-functional teams, with the ability to effectively communicate design trade-offs, schedule progress, and technical outcomes to both design and non-design stakeholders.
Applying AI to daily work and design work flow to improve quality and efficiency.

Skills

TSV interface circuit design
High-speed memory interface design
Timing analysis
Parasitic modeling
Signal integrity
Highly parallel bus performance optimization
Power optimization
Area optimization
Clock distribution
Skew management
EpB optimization
3D-stacked memory architectures
AI application in design workflow

Experience Level

8+ years of relevant experience

Education Level

BS or MS in Electrical Engineering

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all.
With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands.
Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.