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About the Role

Qualcomm Cloud System Hardware Engineering team develops cutting-edge rack level AI inference solutions for next generation liquid-cooled data centers. The team is looking for experienced engineers to join and contribute to the next round of innovative AI products.

Responsibilities

• Design and develop motherboards/add in cards/modules for Qualcomm new AI System on Chip (SoC)/System In Package (SIP).
• Work with cross-functional teams (mechanical, thermal, SI, PTE, regulatory, validation, manufacturing, etc.) for execution of projects from concept to production.
• Support rack level design and integration of cards, servers and networking switches.
• Participate in schematics design, PCB layouts, design reviews, component selections, mechanical and thermal designs, and develop test plans.
• Assist in the development of functional specifications for systems, cards, sub-systems, and rack-level architectures.
• Collaborate with internal teams and ODMs to develop and support customer-specific hardware and system requirements.
• Facilitate consensus on technical trade-offs at hardware, software, and chip design levels.
• Support architecture and card designs including accelerator SoCs, memory, I/O, power delivery, electrical/mechanical integration, and PCB definition/design.
• Participate in the design and development of rack-level inference solutions, ensuring alignment with customer requirements and system-level performance goals.
• Assist in the bring-up and debugging of hardware systems, cards, and rack-level configurations.
• Support factory and manufacturing processes, ensuring quality and consistency across rack-level deployments.
• Travel to development and customer sites as needed to support rack-level solution deployment and validation.

Requirements

• Minimum 5+ years in system/card/rack-level development
• Familiar with rack-level system integration, including chassis, backplane, cabling, airflow, and thermal management across multiple cards/modules.
• Familiarity with rack-scale power delivery, including PDUs, VRMs, PMICs, and power budgeting across multiple boards.
• Experience with rack-level diagnostics and bring-up, including debug of interconnects, signal integrity across long traces/cables, and system-level validation.
• Understanding of rack-level mechanical constraints, EMI shielding, and compliance with data center deployment standards.
• Collaboration with ODMs/OEMs on rack-level design and manufacturing, including review of mechanical drawings, thermal simulations, and compliance testing.
• Knowledge of PCIe cards, motherboards, daughtercards, and backplane signal and power delivery.
• Experience qualifying PMICs, voltage regulators (VRs), clock buffers, flash memory, and connectors for use in complex cards.
• Experience in dense, high-layer count PCB designs (8–20+ layers).
• Familiarity with JTAG tools for bring-up and debug.
• Knowledge of high-speed serial I/O (6–10+ Gbps), PCIe Gen5/6, LPDDR4x/5x, DDR4/5, 200/400/800 GbE.
• Experience with long PCB/cable topologies (0.35–1.5 meter), signal integrity, and compliance with current standards.
• Ability to debug at packet/protocol level across link, transport, transaction, and command layers.
• Experience with LPDDR4x memory technologies, DIMM layout and validation.
• Familiar with clock distribution, power distribution, SMBus, PMBus, SPI, PWM/Tach, and BMC integration.
• Ability to drive schematic capture and PCB layout tools (Cadence Allegro, Mentor Expedition).
• Ability to use lab equipment: oscilloscopes, logic analyzers, JTAG, SMBus, serial debuggers.
• Good understanding of x86 FW/SW stack and firmware architecture.
• Experience with BMC hardware/software integration and management.
• Familiarity with regulatory, environmental, and compliance testing for rack-level systems.
• Familiarity with PCIE switch design/debug and test process
• Familiarity with networking topology
• Experience in Ethernet Switch hardware

Skills

• Schematic design
• PCB layout
• Component selection
• Mechanical design
• Thermal design
• Test plan development
• Functional specification development
• Hardware development
• System requirements development
• Technical trade-off analysis
• Architecture design
• Card design
• Accelerator SoC design
• Memory design
• I/O design
• Power delivery design
• Electrical integration
• Mechanical integration
• PCB definition
• Rack-level solution design
• Hardware bring-up
• Hardware debugging
• Factory process support
• Manufacturing process support
• Rack-level system integration
• Chassis integration
• Backplane integration
• Cabling integration
• Airflow management
• Thermal management
• Power delivery
• PDU management
• VRM management
• PMIC management
• Power budgeting
• Rack-level diagnostics
• Interconnect debugging
• Signal integrity analysis
• System-level validation
• Mechanical constraint analysis
• EMI shielding
• Data center deployment standards
• ODM/OEM collaboration
• Mechanical drawing review
• Thermal simulation
• Compliance testing
• PCIe card design
• Motherboard design
• Daughtercard design
• Backplane design
• Component qualification
• PMIC qualification
• Voltage regulator qualification
• Clock buffer qualification
• Flash memory qualification
• Connector qualification
• High-layer count PCB design
• JTAG tools
• High-speed serial I/O
• PCIe Gen5/6
• LPDDR4x/5x
• DDR4/5
• 200/400/800 GbE
• Long PCB/cable topology
• Packet-level debugging
• Protocol-level debugging
• Link layer debugging
• Transport layer debugging
• Transaction layer debugging
• Command layer debugging
• LPDDR4x memory technology
• DIMM layout
• DIMM validation
• Clock distribution
• Power distribution
• SMBus
• PMBus
• SPI
• PWM/Tach
• BMC integration
• Cadence Allegro
• Mentor Expedition
• Oscilloscope usage
• Logic analyzer usage
• JTAG usage
• SMBus usage
• Serial debugger usage
• x86 FW/SW stack understanding
• Firmware architecture understanding
• BMC hardware integration
• BMC software integration
• Regulatory testing
• Environmental testing
• PCIe switch design
• PCIe switch debug
• PCIe switch test process
• Networking topology
• Ethernet switch hardware

Location

• USA

Work Type

• Full-time

Experience Level

• 5+ years of hardware engineering experience
• 4+ years hardware engineering/Systems development experience
• 2+ years of experience with circuit design
• 2+ years of experience utilizing schematic capture and circuit simulation software
• 2+ years of experience with hardware design and measurement instruments
• 2+ years of Hardware Engineering or related work experience
• 1+ year of Hardware Engineering or related work experience

Education Level

• Bachelor’s degree in Electrical and Electronic Engineering, Computer Engineering, or related field
• Master's Degree in Electrical and Electronic Engineering, Computer Engineering, or related field
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Salary/Compensations

• $111,300.00 - $166,900.00

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package

About the Company

• Qualcomm Technologies, Inc. develops cutting-edge rack level AI inference solutions for next generation liquid-cooled data centers.

Equal Opportunity

• Qualcomm is an equal opportunity employer.
• Qualcomm is committed to providing an accessible process for individuals with disabilities.
• Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
• Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.