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About the Role

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. This role involves reviewing and coordinating work from offshore designers, training junior engineers, and contributing to standard layout methodologies and quality procedures.

Responsibilities

• Remote interfacing with local and global design and layout teams across multiple design centers and time zones.
• Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits.
• Perform schematic-driven layout and design constraints.
• Design die-area efficient layouts according to circuit designer requirements.
• Perform block or top-level layout designs.
• Perform floor-planning, power line planning, shielding, and device-matching layout.
• Verify layouts, passing DRC, LVS, and ERC.
• Contribute to various chip-level routing and layout needs.
• Perform chip level integration, verifications, and tape-out.
• Support other projects as needed by management.
• Train junior layout engineers and offshore layout contractors.
• Contribute to developing common best practices and workflow across all sites.
• Contribute to build process and procedures to achieve high layout quality.

Requirements

• BA/BS Degree in Layout Design or related field or equivalent experience.
• 10 years’ experience with layout design for analog and full-custom digital blocks.
• Experience with TSMC 180nm, 65nm, 22nm and UMC 55nm process technologies.
• Proficient in using layout editing tools in the Cadence Virtuoso design environment.
• Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre.
• Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation.
• Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints.
• Experience in chip-level floor planning and analog block integration.
• Experience with chip level integration, verifications, and tape-out.
• Ability to use productivity-enhancing tools and design scripts to further automate tasks is desirable.
• Must be able to lift, push, and pull up to 5 lbs.

Skills

• Layout Design
• CMOS circuits
• BiCMOS circuits
• Schematic-driven layout
• Design constraints
• Floor-planning
• Power line planning
• Shielding
• Device matching
• DRC verification
• LVS verification
• ERC verification
• Chip-level integration
• Tape-out
• Cadence Virtuoso
• Cadence PVS
• Mentor Calibre
• Parasitic analysis
• Matching
• Crosstalk analysis
• Latch-up
• IR drop analysis
• Electro migration (EM) analysis
• Deep N-well and NTN isolation
• Signal integrity
• Power distribution
• Analog block integration
• Design scripts

Location

• Remote

Work Type

• Remote

Experience Level

• 10 years’ experience
• Sr.

Education Level

• BA/BS Degree in Layout Design or related field or equivalent experience

Salary/Compensations

• Quarterly bonus tied to the achievement of innovation goals
• Equity grants

Benefits

• Comprehensive and highly competitive compensation package
• Quarterly bonus
• Equity grants

About the Company

• SiTime is the Precision Timing company.
• Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability.
• MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience.
• MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.
• Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability.
• With more than 4 billion devices shipped, SiTime is changing the timing industry.

Equal Opportunity

• SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.